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45 lines
583 B
Verilog
45 lines
583 B
Verilog
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`define WIDTH 16
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module addsub_tb;
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parameter tck = 10;
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reg op, oc; // 0: add, 1: sub
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wire [`WIDTH-1:0] y;
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reg [`WIDTH-1:0] a, b;
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reg c_in;
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wire c_out, h_out;
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reg clk;
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addsub dut(
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op, oc, y, a, b, c_in,
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c_out, h_out
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);
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initial begin
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$dumpvars(-1, dut);
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$dumpfile("addsub_tb.vcd");
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end
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always #(tck/2) clk = ~clk;
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integer i, j;
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initial begin
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clk = 0;
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op = 0; oc = 0;
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c_in = 0;
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for (i=0; i<(1<<`WIDTH); i=i+50)
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for (j=0; j<(1<<`WIDTH); j=j+50) begin
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a = i;
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b = j;
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@(negedge clk);
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$display("%h %h : %h %h", c_out, y, a, b);
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end
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$finish;
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end
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endmodule
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