mirror of
https://github.com/pConst/basic_verilog.git
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135 lines
3.4 KiB
Verilog
135 lines
3.4 KiB
Verilog
/*
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Copyright (c) 2004, 2006 Pablo Bleyer Kocik.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. The name of the author may not be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED
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WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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PacoBlaze test
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*/
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`define PACOBLAZE1
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`ifndef TEST_FILE
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`define TEST_FILE "../test/adc_ctrl.rmh"
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`endif
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`ifndef TEST_CYCLES
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`define TEST_CYCLES 1000
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`endif
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`ifndef TEST_IRQ
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`define TEST_IRQ 100
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`endif
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`include "timescale_inc.v"
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`include "pacoblaze_inc.v"
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module pacoblaze1_tb;
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parameter tck = 10, program_cycles = `TEST_CYCLES;
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reg clk, rst, irq; // clock, reset, interrupt request
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wire [`code_depth-1:0] addr; // instruction address
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wire [`operand_width-1:0] pid, pout; // port id, port output
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wire ren, wen; // read strobe, write strobe
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`ifdef HAS_INTERRUPT_ACK
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wire iak; // interrupt acknowledge
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`endif
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reg [`operand_width-1:0] port[0:`port_size-1]; // port memory
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wire [`code_width-1:0] din; // program data input
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wire [`operand_width-1:0] pin = port[pid]; // port input
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/* PacoBlaze program memory */
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blockram #(.width(`code_width), .depth(`code_depth))
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rom(
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.clk(clk),
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.rst(rst),
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.enb(1'b1),
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.wen(1'b0),
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.addr(addr),
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.din(`code_width 'b0),
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.dout(din)
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);
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/* PacoBlaze dut */
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pacoblaze1 dut(
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.clk(clk),
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.reset(rst),
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.address(addr),
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.instruction(din),
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.port_id(pid),
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.read_strobe(ren),
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.write_strobe(wen),
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.in_port(pin),
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.out_port(pout),
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.interrupt(irq)
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`ifdef HAS_INTERRUPT_ACK
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, .interrupt_ack(iak)
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`endif
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);
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/* Clocking device */
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always #(tck/2) clk = ~clk;
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/* Watch port memory */
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always @(posedge clk) if (wen) port[pid] <= pout;
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/* Display code */
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always @(negedge clk)
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if (dut.timing_control)
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`ifdef HAS_DEBUG
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$display("%h:%h %s", addr, din, dut.idu_debug);
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`else
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$display("%h:%h", rom.addr, rom.din);
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`endif
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/* Simulation setup */
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initial begin
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$dumpvars(-1, dut);
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$dumpfile("pacoblaze1_tb.vcd");
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$readmemh(`TEST_FILE, rom.ram);
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end
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/* Simulation */
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integer i;
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initial begin
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for (i=0; i<`port_size; i=i+1) port[i] = i; // initialize ports
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clk = 0; rst = 1; irq = 0;
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#(tck*2);
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@(negedge clk) rst = 0; // free processor
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#(tck*`TEST_IRQ);
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@(negedge clk) irq = 1; // interrupt request
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// @(negedge clk) ;
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@(negedge clk) irq = 0;
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#(program_cycles*tck+100) $finish;
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end
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endmodule
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