mirror of
https://github.com/pConst/basic_verilog.git
synced 2025-01-14 06:42:54 +08:00
36 lines
804 B
Verilog
36 lines
804 B
Verilog
//--------------------------------------------------------------------------------
|
||
// ClkDivider.v
|
||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||
//--------------------------------------------------------------------------------
|
||
|
||
// INFO --------------------------------------------------------------------------------
|
||
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
|
||
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
|
||
|
||
|
||
/*ClkDivider CD1 (
|
||
.clk(),
|
||
.nrst(),
|
||
.out()
|
||
);
|
||
defparam CD1.WIDTH = 32;*/
|
||
|
||
|
||
module ClkDivider(clk,nrst,out);
|
||
|
||
input wire clk;
|
||
input wire nrst;
|
||
output reg [(WIDTH-1):0] out = 0;
|
||
|
||
parameter WIDTH = 32;
|
||
|
||
always @ (posedge clk) begin
|
||
if (~nrst) begin
|
||
out[(WIDTH-1):0] <= 0;
|
||
end
|
||
else begin
|
||
out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
|
||
end
|
||
end
|
||
|
||
endmodule |