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68 lines
1.7 KiB
Verilog
68 lines
1.7 KiB
Verilog
//--------------------------------------------------------------------------------
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// SimplePulseGen.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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/* SimplePulseGen PG1 (
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.clk(),
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.nrst(),
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.low_wdth(),
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.start(),
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.busy(),
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.out()
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); */
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module SimplePulseGen(clk,nrst,low_wdth,start,busy,out);
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input wire clk;
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input wire nrst;
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input wire [31:0] low_wdth;
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input wire start;
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output reg busy = 0;
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output reg out = 0;
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reg [31:0] max_low = 0;
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reg [31:0] cnt_low = 0;
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always @ (posedge clk) begin
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if (~nrst) begin // one and only way to stop SimplePulseGen is to reset it
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max_low[31:0] <= 0;
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cnt_low[31:0] <= 0;
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busy <= 0;
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out <= 0;
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end
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else begin // nrst
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if (~busy) begin
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if (start) begin // buffering input values
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max_low[31:0] <= low_wdth[31:0];
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cnt_low[31:0] <= 0;
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busy <= 1;
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end
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end
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else begin
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if (cnt_low[31:0] < (max_low[31:0]-1)) begin // compensation for firs initialization cycle
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out <= 0;
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cnt_low[31:0] <= cnt_low[31:0] + 1;
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end
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else begin
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if (~out) begin
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out <= 1;
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end
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else begin
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busy <= 0;
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out <= 0;
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end // out
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end // cnt_low
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end // busy
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end // nrst
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end
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endmodule |