Must-have verilog systemverilog modules

Originally published as part of https://github.com/pConst/basic_verilog
by Konstantin Pavlov, pavlovconst@gmail.com

Hi! This is a collection of Verilog SystemVerilog synthesizable modules.

All the code is highly reusable across typical FPGA projects and mainstream FPGA vendors.

Please feel free to make pull requests or contact me in case you spot any code issues.

Also, give me a pleasure, tell me if the code has got succesfully implemented in your hobby, scientific or industrial projects!

Licensing

The code is licensed under CC BY-SA 4_0
That means, that you can remix, transform, and build upon the material for any purpose, even commercially.
However, YOU MUST provide the name of the creator and distribute your contributions under the same license as the original.

Contents description

For your convinience I`ve tagged some sources by their "difficulty":
🟢 - for the most basic tasks
🔴 - for advanced or special purpose routines

If you are a beginner in HW design - you may want to start exploring 🟢 code first.
Almost every source file in the repository contains detailed description and instantiation template!

USAGE	DIRECTORY	DESCRIPTION
	Advanced Synthesis Cookbook/	useful code from Altera's cookbook
	KCPSM6_Release9_30Sept14/	Xilinx's Picoblaze soft processor sources
🔴	XilinxBoardStore_with_Alveo_cards_support	board definitions for Xilinx Alveo accelerator cards
	pacoblaze-2.2/	version of Picoblaze adapted for Altera devices
	avalon_mm_master_templates/	Avalon-MM component templates from Altera
	axi_master_slave_templates/	AXI componet templates generated by Vivado
	benchmark_projects/	benchmarking various IDEs to compile exact same Verilog project
	dual_port_ram_templates/	Block RAM templates
	example_projects/	FPGA project boilerplates and examples
	gitignores/	gitignore files for FPGA projects
	scripts/	useful TCL, batch and shell scripts
🔴	scripts_for_intel_hls/	useful scripts for compiling for Intel HLS
🔴	scripts_for_xilinx_hls/	useful scripts for compiling for Xilinx HLS
	xpm	Xilinx parametrizable macros sources

USAGE	FILE	DESCRIPTION
	adder_tree.sv	adding multiple values together in parallel
	axi4l_logger.sv
🟢	bin2gray.sv	combinational Gray code to binary converter
	bin2pos.sv	converts binary coded value to positional (one-hot) code
	cdc_data.sv
	cdc_strobe.sv
🟢	clk_divider.sv	wide reference clock divider
	clogb2.svh
🟢	debounce.v	two-cycle debounce for input buttons
🟢	delay.sv	useful module to make static delays or to synchronize across clock domains
	delayed_event.sv
	dynamic_delay.sv	dynamic delay for arbitrary input signal
🟢	edge_detect.sv	combinational edge detector, gives one-tick pulses on every signal edge
	encoder.v	digital encoder input logic module
🔴	fast_counter.sv
	fifo_combiner.sv
	fifo_operator.sv
🔴	fifo_single_clock_ram_*.sv	single-clock FIFO buffer (queue) implementation
🔴	fifo_single_clock_reg_*.sv	single-clock FIFO buffer (queue) implementation
🟢	gray2bin.sv	combinational binary to Gray code converter
🔴	gray_functions.vh
🟢	hex2ascii.sv
	leave_one_hot.sv	combinational module that leaves only lowest hot bit
	lifo.sv	single-clock LIFO buffer (stack) implementation
	main_tb.sv	basic testbench template
	moving_average.sv
	pack_unpack_array.v
	pattern_detect.sv
	pdm_modulator.sv
	pos2bin.sv	converts positional (one-hot) value to binary representation
	prbs_gen_chk.sv	PRBS pattern generator or checker
	preview_fifo.sv
	priority_enc.sv
	pulse_gen.sv	generates pulses with given width and delay
	pulse_stretch.sv	configurable pulse stretcher/extender module
	pwm_modulator.sv
🔴	read_ahead_buf.sv
	reset_set.sv	SR trigger variant w/o metastable state, set dominates here
	reset_set_comb.sv
	reverse_bytes.sv	reverses bytes order within multi-byte array
	reverse_dimensions.sv
	reverse_vector.sv	reverses signal order within multi-bit bus
	round_robin_enc.sv
	round_robin_performance_enc.sv
	set_reset.sv	SR trigger variant w/o metastable state, reset dominates here
	set_reset_comb.sv
	sim_clk_gen.sv
🔴	soft_latch.sv
	spi_master.sv	universal spi master module
🔴	true_dual_port_write_first_2_clock_ram.sv
🔴	true_single_port_write_first_ram.sv
	uart_debug_printer.sv
🟢	uart_rx.sv	straightforward yet simple UART receiver
	uart_rx_shifter.sv	UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs
🟢	uart_tx.sv	straightforward yet simple UART transmitter
	uart_tx_shifter.sv	UART-like transmitter shifter for simple synchronous messaging inside the FPGA or between FPGAs

Also added testbenches for selected modules.