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59 lines
1.8 KiB
Verilog
59 lines
1.8 KiB
Verilog
//--------------------------------------------------------------------------------
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// dynamic_delay.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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//
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//
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// WARNING!
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// This is an adapted verilog version of the Dynamic delay module
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// Please use original "dynamic_delay.sv" where it is posibble
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module dynamic_delay #( parameter
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LENGTH = 63, // maximum delay chain length
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WIDTH = 4, // data width
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SEL_W = $clog2( (LENGTH+1)*WIDTH ) // output selector width
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// plus one is for zero delay element
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)(
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input clk,
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input nrst,
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input ena,
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input [WIDTH-1:0] in, // input data
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// bit in[0] is the "oldest" one
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// bit in[WIDTH] is considered the most recent
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input [SEL_W-1:0] sel, // output selector
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output [WIDTH-1:0] out // output data
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);
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reg [(LENGTH+1)*WIDTH-1:WIDTH] data = 0;
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wire [(LENGTH+1)*WIDTH-1:0] pack_data;
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assign pack_data[(LENGTH+1)*WIDTH-1:0] =
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{ data[(LENGTH+1)*WIDTH-1:WIDTH], in[WIDTH-1:0] };
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integer i;
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always@(posedge clk) begin
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if( ~nrst ) begin
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// reset all data except zero element
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for( i=2; i<(LENGTH+2); i=i+1 ) begin
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data[i*WIDTH-1-:WIDTH] <= 0;
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end
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end else if (ena) begin
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for( i=3; i<(LENGTH+2); i=i+1 ) begin
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data[i*WIDTH-1-:WIDTH] <= data[(i-1)*WIDTH-1-:WIDTH];
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end
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// zero element assignment
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data[2*WIDTH-1-:WIDTH] <= in[WIDTH-1:0];
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end
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end
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// output selector, sel==0 gives non-delayed output
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assign out[WIDTH-1:0] = pack_data[sel[SEL_W-1:0]+:WIDTH];
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endmodule
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