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74 lines
2.1 KiB
Systemverilog
74 lines
2.1 KiB
Systemverilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module gearbox_33_32_tb ();
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reg clk,arst;
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reg [32:0] din = 0;
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wire din_ready;
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wire [31:0] dout;
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gearbox_33_32 dut (
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.*
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);
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integer n;
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wire [32:0] recovered;
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wire recovered_valid;
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reg din_slip;
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initial begin
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din_slip = 1'b1;
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for (n=0; n<34; n=n+1) begin
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@(negedge clk);
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end
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din_slip = 1'b0;
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end
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gearbox_32_33 dut_b (
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.clk,.arst,
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.din(dout), // bit 0 is sent first
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.din_valid(1'b1),
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.din_slip(din_slip), // drop bit 0 of the current din
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.dout(recovered), // bit 0 is sent first
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.dout_valid(recovered_valid)
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);
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always @(posedge clk) begin
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if (din_ready) din <= din + 1'b1;
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end
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////////////////////////////////////
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// clock driver
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always begin
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#5 clk = ~clk;
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end
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initial begin
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clk = 0;
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arst = 0;
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#1 arst = 1'b1;
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@(negedge clk) arst = 1'b0;
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end
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endmodule |