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99 lines
3.3 KiB
Verilog
99 lines
3.3 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 02-24-2006
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module in_range (dat,inr);
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`include "log2.inc"
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`include "highest_10.inc"
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parameter LOWER_BOUND = 85;
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parameter UPPER_BOUND = 120;
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parameter WIDTH = 7;
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parameter METHOD = 2;
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// identify the most significant bit where UPPER is 1 and
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// LOWER is 0
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localparam SPLIT_POINT = highest_10 (UPPER_BOUND,LOWER_BOUND);
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input [WIDTH-1:0] dat;
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output inr;
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wire inr;
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genvar i,j;
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generate
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if (METHOD == 0) begin
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////////////////////////////////////////
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// generic implementation
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////////////////////////////////////////
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assign inr = (dat >= LOWER_BOUND && dat < UPPER_BOUND);
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end
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else if (METHOD == 1) begin
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///////////////////////////////////////////////////
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// use of subtractors to implement the comparison
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///////////////////////////////////////////////////
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wire [WIDTH+1:0] result;
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wire [WIDTH:0] comp_a;
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assign comp_a = dat-LOWER_BOUND;
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assign result = comp_a-(UPPER_BOUND-LOWER_BOUND);
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assign inr = result[WIDTH+1];
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end
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else if (METHOD == 2) begin
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///////////////////////////////////////////////////
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// Demonstration of over / under / equal technique
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// illustrated by Paul Q3 2003 slides
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// No hard structure / chains.
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///////////////////////////////////////////////////
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wire ou_out;
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wire eq_out;
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initial begin
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$display ("%x",UPPER_BOUND[SPLIT_POINT-1:0]);
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$display ("%x",LOWER_BOUND[SPLIT_POINT-1:0]);
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$display ("%x",UPPER_BOUND[WIDTH-1:SPLIT_POINT]);
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end
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over_under ou (
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.over(!dat[SPLIT_POINT]),
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.dat(dat[SPLIT_POINT-1:0]),
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.out(ou_out)
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);
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defparam ou .WIDTH = SPLIT_POINT;
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defparam ou .METHOD = 0;
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defparam ou .UPPER_BOUND = UPPER_BOUND [SPLIT_POINT-1 : 0];
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defparam ou .LOWER_BOUND = LOWER_BOUND [SPLIT_POINT-1 : 0];
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equal_const eq (
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.dat(dat[WIDTH-1:SPLIT_POINT+1]),
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.out(eq_out)
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);
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defparam eq .WIDTH = WIDTH-SPLIT_POINT-1;
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defparam eq .CONST_VAL = UPPER_BOUND [WIDTH-1:SPLIT_POINT+1];
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defparam eq .METHOD = 0;
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assign inr = ou_out & eq_out;
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end
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endgenerate
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endmodule |