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121 lines
3.4 KiB
Verilog
121 lines
3.4 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 05-02-2007
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module approx_fp_invsqrt_tb ();
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// number of stimuli in table
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parameter NUM_STIM = 50000;
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// 1st order approximation only v.s. additional Newton refinement round
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parameter CORRECTION_ROUND = 1'b1;
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// the correction round increases the pipeline latency
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parameter LAG = CORRECTION_ROUND ? 6 : 1;
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reg [32*NUM_STIM*7-1:0] test_stim =
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{
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`include "inv_sqrt.tbl"
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};
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reg clk = 0;
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//////////////////////////
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// handle the stimulus and
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// expected result latency
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//////////////////////////
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wire [31:0] in, invsqrt_in, min_err2, max_err2,
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min_err5, max_err5,min_err10, max_err10;
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wire [6*32-1:0] err_bars;
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assign {in,err_bars} = test_stim [7*32-1:0];
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reg [32*6*LAG-1:0] history;
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always @(posedge clk) begin
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history <= (history << 6*32) | err_bars;
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end
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assign {min_err2,max_err2,min_err5,max_err5,min_err10,max_err10} =
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history [LAG*6*32-1:(LAG-1)*6*32];
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//////////////////////////
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// DUT
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//////////////////////////
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approx_fp_invsqrt ais (.clk(clk),.in(in),.out(invsqrt_in));
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defparam ais .CORRECTION_ROUND = CORRECTION_ROUND;
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integer n;
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integer fail10 = 0, fail5 = 0, fail2 = 0;
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initial begin
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for (n=0; n<LAG; n=n+1)
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begin : flush
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@(posedge clk);
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end
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for (n=0; n<NUM_STIM-1; n=n+1)
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begin : tst
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@(posedge clk);
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#5 if (invsqrt_in < min_err10 ||
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invsqrt_in > max_err10)
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begin
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$display ("10pct error bar failed");
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fail10 = fail10 + 1'b1;
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end
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else if (invsqrt_in < min_err5 ||
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invsqrt_in > max_err5)
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begin
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$display ("5pct error bar failed");
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fail5 = fail5 + 1'b1;
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end
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else if (invsqrt_in < min_err2 ||
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invsqrt_in > max_err2)
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begin
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$display ("2pct error bar failed");
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fail2 = fail2 + 1'b1;
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end
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end
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$display ("Total trials %d",NUM_STIM);
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$display (" 2 to 5 pct err %d",fail2);
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$display (" 5 to 10 pct err %d",fail5);
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$display (" over 10 pct err %d",fail10);
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if (fail10 == 0) $display ("PASS");
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$stop();
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end
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always @(posedge clk) begin
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test_stim <= test_stim >> (7*32);
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end
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always begin
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#100 clk = ~clk;
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end
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endmodule
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