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34 lines
771 B
Verilog
34 lines
771 B
Verilog
//--------------------------------------------------------------------------------
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// Synch.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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//
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//
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(* keep_hierarchy = "yes" *) module Synch(clk, in, out);
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input wire clk;
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input wire in;
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output wire out;
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parameter LENGTH = 2; // length of each sincronizer chain
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//parameter WIDTH = 1; // independent channels
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//(* keep = "true" *)
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reg [(LENGTH-1):0] data = 0;
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integer i;
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always @ (posedge clk) begin
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data[0] <= in;
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for (i=1; i<LENGTH; i=i+1) begin
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data[i] <= data[i-1];
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end
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end
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assign
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out = data[LENGTH-1];
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endmodule
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