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203 lines
6.0 KiB
Verilog
203 lines
6.0 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 03-02-2006
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//
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// compute -
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// over ? (dat >= LOWER_BOUND) : (dat < UPPER_BOUND);
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//
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// where upper and lower are constants
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//
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// Building block used for an efficient in-range comparator.
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//
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module over_under (over,dat,out);
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`include "compare_masks.inc"
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parameter WIDTH = 32;
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parameter UPPER_BOUND = 32'hae141234;
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parameter LOWER_BOUND = 32'hae100010;
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parameter METHOD = 3;
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localparam [WIDTH:0] NEG_UPPER = ~UPPER_BOUND + 1;
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localparam NEXT_EVEN_WIDTH = (WIDTH & 1) ? WIDTH + 1 : WIDTH;
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localparam HALF_WIDTH = NEXT_EVEN_WIDTH >> 1;
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input [WIDTH-1:0] dat;
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input over;
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output out;
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// zero pad out the data and constant for convenience
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wire [WIDTH+5:0] ext_dat = {6'b0,dat};
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localparam EXT_LOWER = {6'b0,LOWER_BOUND};
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localparam EXT_UPPER = {6'b0,UPPER_BOUND};
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localparam EXT_NEG_UPPER = {6'b0,NEG_UPPER};
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genvar i;
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generate
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if (METHOD == 0) begin
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///////////////////////
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// Generic style
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///////////////////////
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assign out = over ? (dat >= LOWER_BOUND) : (dat < UPPER_BOUND);
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end
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else if (METHOD == 1) begin
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////////////////////////////////////////
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// Rephrased in terms of add / subtract
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////////////////////////////////////////
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wire [WIDTH:0] chain;
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//assign chain = (over ? (LOWER_BOUND + ~dat) : (dat-UPPER_BOUND));
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//assign chain = (over ? (LOWER_BOUND + ~dat) : (dat + ~UPPER_BOUND + 1));
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//assign chain = (over ? ~dat : dat) + (over ? LOWER_BOUND : ~UPPER_BOUND + 1);
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assign chain = (over ? ~dat : dat) + (over ? LOWER_BOUND : NEG_UPPER);
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assign out = chain[WIDTH];
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end
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else if (METHOD == 2) begin
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////////////////////////////////////////
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// Compress to 2 bits per cell
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// this uses quite a bit of logic in
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// front of the carry chain. Use
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// WYS version to guarantee packing.
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////////////////////////////////////////
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wire [HALF_WIDTH:0] chain;
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wire [HALF_WIDTH-1 :0] g;
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wire [HALF_WIDTH-1 :0] p;
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// rephrase in terms of generate and propagate
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// carry - looking at two bits of the compare at
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// a time.
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for (i=0; i<HALF_WIDTH; i=i+1)
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begin : half
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wire [1:0] dat_bits = {over ^ ext_dat[i*2+1], over ^ ext_dat[i*2]};
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wire [1:0] const_bits = over ? EXT_LOWER [i*2+1:i*2] :
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EXT_NEG_UPPER [i*2+1:i*2];
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assign p [i] = (dat_bits[0] ^ const_bits[0]) &
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(dat_bits[1] ^ const_bits[1]);
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assign g [i] = (dat_bits[1] & const_bits[1]) |
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((dat_bits[0] & const_bits[0]) &
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(dat_bits[1] | const_bits[1]));
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end
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assign chain = (g | p) + g;
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assign out = !chain[HALF_WIDTH];
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end
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else if (METHOD == 3) begin
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////////////////////////////////////////
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// WYSIWYG share chain using 2 bits per cell
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////////////////////////////////////////
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wire [HALF_WIDTH:0] chain;
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wire [HALF_WIDTH+1 : 0] cin;
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wire [HALF_WIDTH+1 : 0] sin;
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assign cin[0] = 1'b0;
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assign sin[0] = 1'b0;
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for (i=0; i<=HALF_WIDTH; i=i+1)
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begin : half
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stratixii_lcell_comb w (
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.dataa(over),
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.datab(1'b1),
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.datac(ext_dat[i*2+0]),
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.datad(ext_dat[i*2+1]),
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// unused
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.datae(1'b0),
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.dataf(1'b0),
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.datag(1'b0),
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.cin(cin[i]),
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.sharein(sin[i]),
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.sumout(chain[i]),
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.cout(cin[i+1]),
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.combout(),
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.shareout(sin[i+1])
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);
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defparam w .shared_arith = "on";
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defparam w .extended_lut = "off";
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defparam w .lut_mask =
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// the 1st cell needs to do >= for over = 1, < for over = 0
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i == 0 ? {
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16'h0000,
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(16'haaaa & dc_ge_const_mask(EXT_LOWER[i*2+1:i*2])) |
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(16'h5555 & dc_less_const_mask(EXT_UPPER[i*2+1:i*2])),
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16'h0000,
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(16'haaaa & dc_eq_const_mask(EXT_LOWER[i*2+1:i*2])) |
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(16'h5555 & dc_eq_const_mask(EXT_UPPER[i*2+1:i*2]))
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}
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// following cells needs to do > for over = 1, < for over = 0
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: {
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16'h0000,
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(16'haaaa & dc_greater_const_mask(EXT_LOWER[i*2+1:i*2])) |
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(16'h5555 & dc_less_const_mask(EXT_UPPER[i*2+1:i*2])),
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16'h0000,
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(16'haaaa & dc_eq_const_mask(EXT_LOWER[i*2+1:i*2])) |
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(16'h5555 & dc_eq_const_mask(EXT_UPPER[i*2+1:i*2]))
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};
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end
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// this carry out routing track cannot directly
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// fanout to other cells, it needs another cell
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// to leave the chain.
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// equiv to assign out = cin[HALF_WIDTH+1];
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stratixii_lcell_comb tail (
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.dataa(1'b1),
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.datab(1'b1),
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.datac(1'b1),
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.datad(1'b1),
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// unused
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.datae(1'b0),
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.dataf(1'b0),
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.datag(1'b0),
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.cin(cin[HALF_WIDTH+1]),
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.sharein(sin[HALF_WIDTH+1]),
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.sumout(out),
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.cout(),
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.combout(),
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.shareout()
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);
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defparam tail .shared_arith = "on";
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defparam tail .extended_lut = "off";
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defparam tail .lut_mask = {
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16'h0000,
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16'hffff,
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16'h0000,
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16'h0000
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};
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end
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endgenerate
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endmodule
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