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80 lines
2.2 KiB
Verilog
80 lines
2.2 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 02-23-2006
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module pipe_equal_tb ();
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reg [63:0] ra;
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reg [63:0] rb;
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reg clk,rst,fail;
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initial begin
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ra = 0;
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rb = 0;
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fail = 0;
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clk = 0;
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rst = 0;
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#10 rst = 1;
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#10 rst = 0;
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#100000
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if (!fail) $display ("PASS");
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$stop();
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end
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wire eq;
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reg [2:0] lag;
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always @(posedge clk) begin
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lag <= (lag << 1) | (ra == rb);
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end
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pipe_equal p (.rst(rst),.clk(clk),.a(ra),.b(rb),.eq(eq));
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always begin
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#100 clk = ~clk;
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end
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// make the inputs equal a lot of the time
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always @(negedge clk) begin
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if ($random & 1'b1) begin
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ra = {$random,$random};
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rb = {$random,$random};
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end
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else begin
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rb = ra;
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end
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end
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// check it
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always @(posedge clk) begin
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#10 if (lag[2] == 1'b1 || lag[2] == 1'b0) begin
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if (lag[2] != eq) begin
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$display ("Mismatch at time %d",$time);
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fail = 1;
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end
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end
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end
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endmodule
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