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110 lines
3.0 KiB
Verilog
110 lines
3.0 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// liu - 07-16-2007
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module approx_fp_div (a, b, q, clk);
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input [31:0] a, b;
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input clk;
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output [31:0] q;
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reg a_sign, b_sign, q_sign;
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reg [7:0] a_exp, b_exp, q_exp;
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reg [22:0] a_frac, q_frac;
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reg [5:0] b_frac /*synthesis keep*/;
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//input, output interface
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always @ (posedge clk)
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begin
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a_sign <= a[31];
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a_exp <= a[30:23];
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a_frac <= a[22:0];
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b_sign <= b[31];
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b_exp <= b[30:23];
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b_frac <= b[22:17];
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end
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//stage 1
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//sign bit and exp
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reg q_sign_reg1;
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reg [7:0] q_exp_reg1;
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always @ (posedge clk)
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begin
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q_sign_reg1 <= a_sign ^ b_sign;
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q_exp_reg1 <= {1'b0, a_exp} + 9'h7e - {1'b0, b_exp};
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end
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//frac bits
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wire [23:0] a0_tmp;
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assign a0_tmp = {1'b1, a_frac};
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//Get estimation e0
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reg [6:0] e0_reg1;
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wire [6:0] e0 /*synthesis keep*/;
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reg [23:0] a0_reg1;
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always @ (posedge clk)
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begin
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e0_reg1 <= e0;
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a0_reg1 <= a0_tmp;
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end
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approx_fp_div_lut tbl1(.in(b_frac), .out(e0));
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//Stage 2
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//Product
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wire [31:0] product;
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reg q_sign_reg2, q_sign_reg3, q_sign_reg4;
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reg [7:0] q_exp_reg2, q_exp_reg3, q_exp_reg4, q_exp_plus;
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always @ (posedge clk)
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begin
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q_sign_reg2 <= q_sign_reg1;
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q_sign_reg3 <= q_sign_reg2;
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q_sign_reg4 <= q_sign_reg3;
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q_exp_reg2 <= q_exp_reg1;
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q_exp_reg3 <= q_exp_reg2;
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q_exp_reg4 <= q_exp_reg3;
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q_exp_plus <= q_exp_reg3 + 1'b1;
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end
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mult_3tick mult1(
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.clk(clk),
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.a_in({12'b0,a0_reg1}),
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.b_in({29'b1,e0_reg1}),
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.o(product));
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//Stage3
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wire [22:0] q_frac_tmp;
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assign q_frac_tmp = (product[31])? product[30:8] : product[29:7];
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always @(posedge clk)
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begin
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q_sign <= q_sign_reg4;
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q_exp <= (product[31])? q_exp_plus : q_exp_reg4;
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q_frac <= q_frac_tmp;
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end
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assign q = {q_sign, q_exp, q_frac};
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endmodule
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