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397 lines
12 KiB
Verilog
397 lines
12 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 06-11-2007
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// Latency 3 pipelined DSP block based multiplier.
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// input width up to 36x36 with input, output, and pipeline registers.
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//
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// This was derived from a pipelined LPM MULT VQM.
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// The awkward flow is necessary to be super explicit about
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// where the registers are intended to be. The tools
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// are too clever for their own good sometimes.
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//
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module mult_3tick (
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clk,
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a_in,
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b_in,
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o
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);
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parameter IN_WIDTH = 36;
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parameter OUT_WIDTH = 2 * IN_WIDTH;
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input clk;
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input [IN_WIDTH-1:0] a_in, b_in;
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output [OUT_WIDTH-1:0] o;
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// ENHANCEMENT - shift these left
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wire [35:0] a = 36'b0 | a_in;
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wire [35:0] b = 36'b0 | b_in;
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wire [71:0] o_int;
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assign o = o_int[OUT_WIDTH-1:0];
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wire gnd;
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wire vcc;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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wire [35:0] mult1_out;
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stratixii_mac_mult mult1_i (
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.signa(gnd),
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.signb(gnd),
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.sourcea(gnd),
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.sourceb(gnd),
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.round(gnd),
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.saturate(gnd),
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.dataa({a[17:0]}),
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.datab({b[17:0]}),
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.clk({clk_unconnected_wire_0,clk_unconnected_wire_1,clk_unconnected_wire_2,clk}),
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.aclr({gnd,gnd,gnd,gnd}),
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.ena({vcc,vcc,vcc,vcc}),
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.scanina(18'b0),
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.scaninb(18'b0),
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.scanouta(),
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.scanoutb(),
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// synthesis translate off
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// simulation only ports
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.devpor(1'b1),
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.devclrn(1'b1),
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.zeroacc(1'b0),
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.mode(1'b0),
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// synthesis translate on
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.dataout(mult1_out[35:0])
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// .observabledataa_regout(),
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// .observabledatab_regout());
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);
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defparam mult1_i .dataa_width = 18;
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defparam mult1_i .datab_width = 18;
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defparam mult1_i .dataa_clock = "0";
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defparam mult1_i .datab_clock = "0";
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defparam mult1_i .signa_clock = "none";
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defparam mult1_i .signb_clock = "none";
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defparam mult1_i .dataa_clear = "0";
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defparam mult1_i .datab_clear = "0";
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defparam mult1_i .signa_clear = "none";
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defparam mult1_i .signb_clear = "none";
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defparam mult1_i .output_clock = "0";
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defparam mult1_i .output_clear = "0";
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defparam mult1_i .round_clock = "none";
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defparam mult1_i .round_clear = "none";
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defparam mult1_i .saturate_clock = "none";
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defparam mult1_i .saturate_clear = "none";
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defparam mult1_i .mode_clock = "none";
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defparam mult1_i .zeroacc_clock = "none";
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defparam mult1_i .mode_clear = "none";
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defparam mult1_i .zeroacc_clear = "none";
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defparam mult1_i .dynamic_mode = "no";
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defparam mult1_i .bypass_multiplier = "no";
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defparam mult1_i .signa_internally_grounded = "true";
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defparam mult1_i .signb_internally_grounded = "true";
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wire [35:0] mult2_out;
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stratixii_mac_mult mult2_i (
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.signa(gnd),
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.signb(gnd),
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.sourcea(gnd),
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.sourceb(gnd),
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.round(gnd),
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.saturate(gnd),
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.dataa(a[35:18]),
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.datab(b[35:18]),
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.clk({clk_unconnected_wire_3,clk_unconnected_wire_4,clk_unconnected_wire_5,clk}),
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.aclr({gnd,gnd,gnd,gnd}),
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.ena({vcc,vcc,vcc,vcc}),
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.scanina(18'b0),
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.scaninb(18'b0),
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.scanouta(),
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.scanoutb(),
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// synthesis translate off
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// simulation only ports
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.devpor(1'b1),
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.devclrn(1'b1),
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.zeroacc(1'b0),
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.mode(1'b0),
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// synthesis translate on
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.dataout(mult2_out[35:0])
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// .observabledataa_regout(),
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// .observabledatab_regout());
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);
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defparam mult2_i .dataa_width = 18;
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defparam mult2_i .datab_width = 18;
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defparam mult2_i .dataa_clock = "0";
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defparam mult2_i .datab_clock = "0";
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defparam mult2_i .signa_clock = "none";
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defparam mult2_i .signb_clock = "none";
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defparam mult2_i .dataa_clear = "0";
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defparam mult2_i .datab_clear = "0";
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defparam mult2_i .signa_clear = "none";
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defparam mult2_i .signb_clear = "none";
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defparam mult2_i .output_clock = "0";
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defparam mult2_i .output_clear = "0";
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defparam mult2_i .round_clock = "none";
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defparam mult2_i .round_clear = "none";
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defparam mult2_i .saturate_clock = "none";
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defparam mult2_i .saturate_clear = "none";
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defparam mult2_i .mode_clock = "none";
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defparam mult2_i .zeroacc_clock = "none";
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defparam mult2_i .mode_clear = "none";
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defparam mult2_i .zeroacc_clear = "none";
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defparam mult2_i .dynamic_mode = "no";
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defparam mult2_i .bypass_multiplier = "no";
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defparam mult2_i .signa_internally_grounded = "false";
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defparam mult2_i .signb_internally_grounded = "false";
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wire [35:0] mult3_out;
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stratixii_mac_mult mult3_i (
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.signa(gnd),
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.signb(gnd),
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.sourcea(gnd),
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.sourceb(gnd),
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.round(gnd),
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.saturate(gnd),
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.dataa(a[35:18]),
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.datab(b[17:0]),
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.clk({clk_unconnected_wire_6,clk_unconnected_wire_7,clk_unconnected_wire_8,clk}),
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.aclr({gnd,gnd,gnd,gnd}),
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.ena({vcc,vcc,vcc,vcc}),
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.scanina(18'b0),
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.scaninb(18'b0),
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.scanouta(),
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.scanoutb(),
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// synthesis translate off
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// simulation only ports
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.devpor(1'b1),
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.devclrn(1'b1),
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.zeroacc(1'b0),
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.mode(1'b0),
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// synthesis translate on
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.dataout(mult3_out[35:0])
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// .observabledataa_regout(),
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// .observabledatab_regout());
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);
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defparam mult3_i .dataa_width = 18;
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defparam mult3_i .datab_width = 18;
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defparam mult3_i .dataa_clock = "0";
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defparam mult3_i .datab_clock = "0";
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defparam mult3_i .signa_clock = "none";
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defparam mult3_i .signb_clock = "none";
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defparam mult3_i .dataa_clear = "0";
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defparam mult3_i .datab_clear = "0";
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defparam mult3_i .signa_clear = "none";
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defparam mult3_i .signb_clear = "none";
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defparam mult3_i .output_clock = "0";
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defparam mult3_i .output_clear = "0";
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defparam mult3_i .round_clock = "none";
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defparam mult3_i .round_clear = "none";
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defparam mult3_i .saturate_clock = "none";
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defparam mult3_i .saturate_clear = "none";
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defparam mult3_i .mode_clock = "none";
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defparam mult3_i .zeroacc_clock = "none";
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defparam mult3_i .mode_clear = "none";
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defparam mult3_i .zeroacc_clear = "none";
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defparam mult3_i .dynamic_mode = "no";
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defparam mult3_i .bypass_multiplier = "no";
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defparam mult3_i .signa_internally_grounded = "false";
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defparam mult3_i .signb_internally_grounded = "true";
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wire [35:0] mult4_out;
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stratixii_mac_mult mult4_i (
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.signa(gnd),
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.signb(gnd),
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.sourcea(gnd),
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.sourceb(gnd),
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.round(gnd),
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.saturate(gnd),
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.dataa(a[17:0]),
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.datab(b[35:18]),
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.clk({clk_unconnected_wire_9,clk_unconnected_wire_10,clk_unconnected_wire_11,clk}),
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.aclr({gnd,gnd,gnd,gnd}),
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.ena({vcc,vcc,vcc,vcc}),
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.scanina(18'b0),
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.scaninb(18'b0),
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.scanouta(),
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.scanoutb(),
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// synthesis translate off
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// simulation only ports
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.devpor(1'b1),
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.devclrn(1'b1),
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.zeroacc(1'b0),
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.mode(1'b0),
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// synthesis translate on
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.dataout(mult4_out[35:0])
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// .observabledataa_regout(),
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// .observabledatab_regout());
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);
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defparam mult4_i .dataa_width = 18;
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defparam mult4_i .datab_width = 18;
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defparam mult4_i .dataa_clock = "0";
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defparam mult4_i .datab_clock = "0";
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defparam mult4_i .signa_clock = "none";
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defparam mult4_i .signb_clock = "none";
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defparam mult4_i .dataa_clear = "0";
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defparam mult4_i .datab_clear = "0";
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defparam mult4_i .signa_clear = "none";
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defparam mult4_i .signb_clear = "none";
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defparam mult4_i .output_clock = "0";
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defparam mult4_i .output_clear = "0";
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defparam mult4_i .round_clock = "none";
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defparam mult4_i .round_clear = "none";
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defparam mult4_i .saturate_clock = "none";
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defparam mult4_i .saturate_clear = "none";
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defparam mult4_i .mode_clock = "none";
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defparam mult4_i .zeroacc_clock = "none";
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defparam mult4_i .mode_clear = "none";
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defparam mult4_i .zeroacc_clear = "none";
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defparam mult4_i .dynamic_mode = "no";
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defparam mult4_i .bypass_multiplier = "no";
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defparam mult4_i .signa_internally_grounded = "true";
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defparam mult4_i .signb_internally_grounded = "false";
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stratixii_mac_out out5 (
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.multabsaturate(gnd),
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.multcdsaturate(gnd),
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.signa(gnd),
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.signb(gnd),
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.dataa(mult1_out),
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.datab(mult2_out),
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.datac(mult3_out),
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.datad(mult4_out),
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.clk({clk_unconnected_wire_9,clk_unconnected_wire_10,clk_unconnected_wire_11,clk}),
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.aclr({gnd,gnd,gnd,gnd}),
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.ena({vcc,vcc,vcc,vcc}),
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// synthesis translate off
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// simulation only ports
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.saturate(1'b0),
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.saturate1(1'b0),
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.devpor(1'b1),
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.devclrn(1'b1),
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.zeroacc(1'b0),
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.zeroacc1(1'b0),
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.mode0(1'b0),
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.mode1(1'b0),
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.accoverflow(),
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// synthesis translate on
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.round0(1'b0),
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.round1(1'b0),
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.addnsub0(1'b0),
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.addnsub1(1'b0),
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.dataout(o_int));
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defparam out5 .operation_mode = "36_bit_multiply";
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defparam out5 .dataa_width = 36;
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defparam out5 .datab_width = 36;
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defparam out5 .datac_width = 36;
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defparam out5 .datad_width = 36;
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defparam out5 .addnsub0_clock = "none";
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defparam out5 .addnsub1_clock = "none";
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defparam out5 .addnsub0_pipeline_clock = "none";
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defparam out5 .addnsub1_pipeline_clock = "none";
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defparam out5 .addnsub0_clear = "none";
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defparam out5 .addnsub1_clear = "none";
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defparam out5 .addnsub0_pipeline_clear = "none";
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defparam out5 .addnsub1_pipeline_clear = "none";
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defparam out5 .round0_clock = "none";
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defparam out5 .round1_clock = "none";
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defparam out5 .round0_pipeline_clock = "none";
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defparam out5 .round1_pipeline_clock = "none";
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defparam out5 .round0_clear = "none";
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defparam out5 .round1_clear = "none";
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defparam out5 .round0_pipeline_clear = "none";
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defparam out5 .round1_pipeline_clear = "none";
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defparam out5 .saturate_clock = "none";
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defparam out5 .multabsaturate_clock = "none";
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defparam out5 .multcdsaturate_clock = "none";
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defparam out5 .saturate_pipeline_clock = "none";
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defparam out5 .multabsaturate_pipeline_clock = "none";
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defparam out5 .multcdsaturate_pipeline_clock = "none";
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defparam out5 .saturate_clear = "none";
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defparam out5 .multabsaturate_clear = "none";
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defparam out5 .multcdsaturate_clear = "none";
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defparam out5 .saturate_pipeline_clear = "none";
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defparam out5 .multabsaturate_pipeline_clear = "none";
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defparam out5 .multcdsaturate_pipeline_clear = "none";
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defparam out5 .mode0_clock = "none";
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defparam out5 .mode1_clock = "none";
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defparam out5 .zeroacc1_clock = "none";
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defparam out5 .saturate1_clock = "none";
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defparam out5 .mode0_pipeline_clock = "none";
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defparam out5 .mode1_pipeline_clock = "none";
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defparam out5 .zeroacc1_pipeline_clock = "none";
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defparam out5 .saturate1_pipeline_clock = "none";
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defparam out5 .mode0_clear = "none";
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defparam out5 .mode1_clear = "none";
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defparam out5 .zeroacc1_clear = "none";
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defparam out5 .saturate1_clear = "none";
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defparam out5 .mode0_pipeline_clear = "none";
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defparam out5 .mode1_pipeline_clear = "none";
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defparam out5 .zeroacc1_pipeline_clear = "none";
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defparam out5 .saturate1_pipeline_clear = "none";
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defparam out5 .output1_clock = "none";
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defparam out5 .output2_clock = "none";
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defparam out5 .output3_clock = "none";
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defparam out5 .output4_clock = "none";
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defparam out5 .output5_clock = "none";
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defparam out5 .output6_clock = "none";
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defparam out5 .output7_clock = "none";
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defparam out5 .output1_clear = "none";
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defparam out5 .output2_clear = "none";
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defparam out5 .output3_clear = "none";
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defparam out5 .output4_clear = "none";
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defparam out5 .output5_clear = "none";
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defparam out5 .output6_clear = "none";
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defparam out5 .output7_clear = "none";
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defparam out5 .dataa_forced_to_zero = "no";
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defparam out5 .datac_forced_to_zero = "no";
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defparam out5 .output_clock = "0";
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defparam out5 .zeroacc_clock = "none";
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defparam out5 .signa_clock = "none";
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defparam out5 .signb_clock = "none";
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defparam out5 .zeroacc_pipeline_clock = "none";
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defparam out5 .signa_pipeline_clock = "none";
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defparam out5 .signb_pipeline_clock = "none";
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defparam out5 .zeroacc_clear = "none";
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defparam out5 .signa_clear = "none";
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defparam out5 .signb_clear = "none";
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defparam out5 .output_clear = "0";
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defparam out5 .zeroacc_pipeline_clear = "none";
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defparam out5 .signa_pipeline_clear = "none";
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defparam out5 .signb_pipeline_clear = "none";
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endmodule
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