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82 lines
2.5 KiB
Verilog
82 lines
2.5 KiB
Verilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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// baeckler - 09-17-2008
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// 58 bit loadable LFSR - x^58 + x^39 + 1
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// with 64 bit output for use as a scrambler
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module scrambler_lfsr (
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input clk, arst,
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input verify,
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input load,
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input [57:0] load_d,
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input evolve,
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output [63:0] q,
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output verify_fail,
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output verify_pass
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);
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// the RESET_VAL must be non-zero and
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// for noise should be unique per TX lane
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parameter RESET_VAL = 58'h1234567_89abcdef;
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reg [57:0] lfsr;
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wire [63:0] next;
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assign q = {lfsr[57:0], next[63:58]};
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// This is from the Interlaken scrambler sample
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// Verilog, regrouped to words.
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assign next = {lfsr,lfsr[57:52]} ^
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{lfsr[38:0],lfsr[38:14]} ^
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{39'b0,lfsr[57:39],6'b0};
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always @(posedge clk or posedge arst) begin
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if(arst) begin
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lfsr <= RESET_VAL;
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end else begin
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if (load) lfsr <= load_d;
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else if (evolve) lfsr <= next[57:0];
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end
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end
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reg last_verify, match;
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always @(posedge clk or posedge arst) begin
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if(arst) begin
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last_verify <= 1'b0;
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match <= 1'b0;
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end
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else begin
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last_verify <= verify;
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match <= (lfsr == load_d);
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end
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end
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assign verify_fail = last_verify & !match;
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assign verify_pass = last_verify & match;
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endmodule
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