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111 lines
3.2 KiB
Verilog
111 lines
3.2 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 05-07-2007
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module pipelined_word_mux_tb ();
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`include "log2.inc"
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parameter WORD_LEN = 16;
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parameter NUM_WORDS_IN = 32; // power of 2
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parameter SEL_PER_LAYER = 2; // output layer may be less
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parameter LATENCY = 3;
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// Quick test cases -
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//
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// 16 words, 2 sel per layer, latency is 2
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// 32 words, 2 sel per layer, latency is 3
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// 64 words, 2 sel per layer, latency is 3
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// 64 words, 3 sel per layer, latency is 2
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parameter NUM_SEL = log2(NUM_WORDS_IN-1);
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parameter BALANCE_SELECTS = 1'b1; // adjust select latency to follow data?
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reg clk,rst;
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reg [NUM_SEL-1:0] sel;
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reg [WORD_LEN*NUM_WORDS_IN-1:0] din;
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wire [WORD_LEN-1:0] dout;
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/////////////////////////////////////////////////
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// DUT
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/////////////////////////////////////////////////
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pipelined_word_mux p (
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.clk(clk),
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.rst(rst),
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.sel(sel),
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.ena(1'b1),
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.din(din),
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.dout(dout));
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defparam p .WORD_LEN = WORD_LEN;
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defparam p .NUM_WORDS_IN = NUM_WORDS_IN;
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defparam p .SEL_PER_LAYER = SEL_PER_LAYER;
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defparam p .BALANCE_SELECTS = BALANCE_SELECTS;
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/////////////////////////////////////////////////
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// functional model
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/////////////////////////////////////////////////
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wire [WORD_LEN-1:0] dout_b, dout_b_lag;
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assign dout_b = din >> (sel * WORD_LEN);
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reg [WORD_LEN*LATENCY-1:0] history;
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always @(posedge clk) begin
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history <= (history << WORD_LEN) | dout_b[WORD_LEN-1:0];
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end
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assign dout_b_lag = history[WORD_LEN*LATENCY-1:WORD_LEN*LATENCY-WORD_LEN];
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/////////////////////////////////////////////////
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// test
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/////////////////////////////////////////////////
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reg fail;
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initial begin
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clk = 0;
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rst = 0;
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din = 0;
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sel = 0;
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fail = 0;
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#1000000 if (!fail) $display ("PASS");
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$stop();
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end
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always begin
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#100 clk = ~clk;
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end
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always @(posedge clk) begin
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din <= (din << 64) | {$random,$random};
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sel <= $random;
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#5 if (dout_b_lag !== dout) begin
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$display ("Mismatch at time %d",$time);
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fail = 1'b1;
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end
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end
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endmodule
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