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102 lines
2.6 KiB
Systemverilog
102 lines
2.6 KiB
Systemverilog
// Copyright 2010 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps/1 ps
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module mlab_dcfifo_tb ();
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parameter LABS_WIDE = 1;
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reg arst = 1'b0;
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reg wrclk = 0;
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reg [LABS_WIDE*20-1:0] real_wrdata = 0;
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reg wrreq = 1'b0;
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wire wrfull;
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reg rdclk = 0;
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wire [LABS_WIDE*20-1:0] rddata;
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reg [LABS_WIDE*20-1:0] last_rddata = 0;
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reg rdreq = 1'b0;
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wire rdempty;
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wire [5:0] rdused;
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wire [5:0] wrused;
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wire parity_err;
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///////////////////
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// simple stim + check
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wire [LABS_WIDE*20-1:0] wrdata = wrreq ? real_wrdata : 0;
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always @(posedge wrclk) begin
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wrreq <= !wrfull & $random & $random;
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if (wrreq) real_wrdata <= real_wrdata + 1'b1;
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end
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always @(posedge rdclk) begin
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rdreq <= (|rdused[5:2]) & $random & !rdreq;
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end
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reg fail = 0;
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reg last_rdreq = 1'b0;
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reg last2_rdreq = 1'b0;
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always @(posedge rdclk) begin
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last_rdreq <= rdreq;
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last2_rdreq <= last_rdreq;
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if (last2_rdreq) begin
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last_rddata <= rddata;
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if (rddata !== (last_rddata + 1'b1)) begin
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$display ("Mismatch at time %d",$time);
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fail = 1'b1;
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end
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end
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end
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//////////////
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mlab_dcfifo dut (.*);
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defparam dut .LABS_WIDE = LABS_WIDE;
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//////////////
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initial begin
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arst = 1'b0;
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#1 arst = 1'b1;
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#100 arst = 1'b0;
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end
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always begin
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#1600 wrclk = ~wrclk;
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end
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always begin
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#1900 rdclk = ~rdclk;
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end
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initial begin
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#10000000 if (!fail) $display ("PASS");
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$stop();
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end
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endmodule
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