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83 lines
2.4 KiB
Verilog
83 lines
2.4 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 12-18-2006
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module ram_delay_reg_tb ();
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parameter DEPTH = 5;
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parameter WIDTH = 64;
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reg clock,enable, fail;
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reg [WIDTH-1:0] data_in;
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wire [WIDTH-1:0] data_out;
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/////////////////////
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// test unit
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/////////////////////
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ram_delay_reg dut (
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.clock (clock),
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.enable (enable),
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.data_in (data_in),
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.data_out (data_out)
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);
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defparam dut .DEPTH = DEPTH;
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defparam dut .WIDTH = WIDTH;
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/////////////////////
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// reference unit
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/////////////////////
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reg [DEPTH*WIDTH-1:0] comp_reg;
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always @(posedge clock) begin
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if (enable) comp_reg <= (comp_reg << WIDTH) | data_in;
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end
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/////////////////////
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// stimulus
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/////////////////////
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initial begin
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clock = 1'b0;
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data_in = 0;
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enable = 1'b1;
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fail = 0;
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#1000000
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if (!fail) $display ("PASS");
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$stop();
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end
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always begin
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#100 clock = ~clock;
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end
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always @(negedge clock) begin
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data_in = {$random,$random};
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enable = $random;
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end
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always @(posedge clock) begin
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#10 if (comp_reg[DEPTH*WIDTH-1:DEPTH*WIDTH-WIDTH] != data_out) begin
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$display ("Disagreement at time %d",$time);
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fail = 1;
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end
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end
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endmodule |