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basic_verilog/scripts/export_autoplaced_pins.tcl
2021-08-09 16:19:16 +03:00

24 lines
815 B
Tcl
Executable File

#------------------------------------------------------------------------------
# export_autoplaced_pins.tcl
# Konstantin Pavlov, pavlovconst@gmail.com
#------------------------------------------------------------------------------
# INFO ------------------------------------------------------------------------
# Use this script for Xilinx Vivado environment to export automaticaly
# placed pins after succesful implementation
#
# Source this script from the TCL Console, after opening implemented design
set f [open export.xdc a]
set my_ports [get_ports]
foreach port_i $my_ports {
puts $f "set_property PACKAGE_PIN [get_property PACKAGE_PIN $port_i] \[get_ports $port_i \] "
}
foreach port_i $my_ports {
puts $f "set_property IOSTANDARD [get_property IOSTANDARD $port_i] \[get_ports $port_i \] "
}
close $f