mirror of
https://github.com/pConst/basic_verilog.git
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95 lines
2.4 KiB
Makefile
95 lines
2.4 KiB
Makefile
#
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# PacoBlaze Makefile
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#
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# Path for the Xilinx sources
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XILINX = ../xilinx
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# Xilinx implementation of PicoBlaze
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KCPSM2 = $(XILINX)/kcpsm2.v
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KCPSM3 = $(XILINX)/kcpsm3.v
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UNISIMS = $(wildcard $(XILINX)/unisims/*.v)
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# Verilog engine
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VERILOG = cver
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#VERILOG = iverilog
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# Icarus Verilog processed verilog file
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VVP = vvp
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# Verilog to HTML
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V2HTML = v2html
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# Instance of PacoBlaze we want to use
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PACOBLAZE = PACOBLAZE3
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# The test file used to run simulation testbenches
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TEST_FILE = "../test/adc_ctrl.rmh"
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# Number of clock cycles to run the simulation
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TEST_CYCLES = 2000
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# Clock cycle where to assert the interrupt request to the uC
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TEST_IRQ = 100
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# Command line for Cver
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ifeq ($(VERILOG),cver)
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VDEF = +define+HAS_DEBUG +define+TEST_FILE="\"$(TEST_FILE)\"" +define+TEST_CYCLES=$(TEST_CYCLES) +define+TEST_IRQ=$(TEST_IRQ) +define+USE_ONEHOT_ENCODING # +define+$(PACOBLAZE)
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endif
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# Command line for Icarus
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ifeq ($(VERILOG),iverilog)
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VDEF = -DHAS_DEBUG -DTEST_FILE="\"$(TEST_FILE)\"" -DTEST_CYCLES=$(TEST_CYCLES) -DTEST_IRQ=$(TEST_IRQ) -DUSE_ONEHOT_ENCODING # -D$(PACOBLAZE)
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endif
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# Flags for v2html
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V2HTMLFLAGS = -m "pablo.N@SPAM.bleyer.org" -htf -ni -h index.html -s -tab 2
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.SECONDARY: .vcd
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# Main target
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all: pacoblaze3_tb.vcd
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# Cver rules
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pacoblaze_idu_tb.vcd: pacoblaze3.v pacoblaze_idu_tb.v
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pacoblaze_dregister_tb.vcd: pacoblaze_dregister.v pacoblaze_dregister_tb.v
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pacoblaze1_tb.vcd: blockram.v pacoblaze1.v pacoblaze1_tb.v
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pacoblaze3_tb.vcd: blockram.v pacoblaze3.v pacoblaze3_tb.v
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pacoblaze3b_tb.vcd: blockram.v pacoblaze3.v pacoblaze3b_tb.v
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compare3_tb.vcd: blockram.v pacoblaze3.v $(KCPSM3) $(UNISIMS) compare3_tb.v
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cmprnd3_tb.vcd: blockram.v pacoblaze3.v $(KCPSM3) $(UNISIMS) cmprnd3_tb.v
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compare3m_tb.vcd: blockram.v pacoblaze3m.v $(KCPSM3) $(UNISIMS) compare3m_tb.v
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pacoblaze3m_tb.vcd: blockram.v pacoblaze3m.v pacoblaze3m_tb.v
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addsub_tb.vcd: addsub.v addsub_tb.v
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# Icarus rules
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pacoblaze3_tb.vvp: blockram.v pacoblaze3.v pacoblaze3_tb.v
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# Make the Verilog code documentation with v2html
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doc: $(wildcard *.v)
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-mkdir doc
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cp $^ doc
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cd doc; $(V2HTML) $(V2HTMLFLAGS) $^
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# Create a value change dump (vcd) file from a verilog source
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%.vcd: %.v
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$(VERILOG) $(VDEF) $^
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# Create an Icarus processed file from a verilog source
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%.vvp: %.v
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$(VERILOG) -o $@ $^
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# Create a value change dump (vcd) file from an Icarus vvp
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%.vcd: %.vvp
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$(VVP) $^
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# Clean simulation and intermediate files
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clean:
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$(RM) *.vvp *.vcd
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# Clean everything
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distclean: clean
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$(RM) *.bak
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$(RM) -r doc
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