FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00
Code Issues Releases Wiki Activity
basic_verilog/example_projects/testbench_template_tb/compile.bat
Konstantin Pavlov b87a6bfad0 Added testbench template
2021-11-01 14:47:08 +03:00

1 line
28 B
Batchfile
Executable File
Raw Blame History

modelsim.exe -do compile.tcl
Reference in New Issue View Git Blame Copy Permalink