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65 lines
1.4 KiB
Verilog
65 lines
1.4 KiB
Verilog
//--------------------------------------------------------------------------------
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// DeBounce.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Debounce for two inpus signal samples. Signal may and maynot be periodic
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// Switches up and down with 3 ticks delay
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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DeBounce DB1 (
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.clk(),
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.nrst( 1'b1 ),
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.en( 1'b1 ),
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.in(),
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.out()
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);
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defparam DB1.WIDTH = 1;
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--- INSTANTIATION TEMPLATE END ---*/
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module DeBounce(clk,nrst,en,in,out);
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input wire clk;
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input wire nrst;
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input wire en;
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input wire [(WIDTH-1):0] in;
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output wire [(WIDTH-1):0] out; // also "present state"
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parameter WIDTH = 1;
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reg [(WIDTH-1):0] d1 = 0;
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reg [(WIDTH-1):0] d2 = 0;
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always @ (posedge clk) begin
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if (~nrst) begin
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d1[(WIDTH-1):0] <= 0;
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d2[(WIDTH-1):0] <= 0;
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end
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else begin
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if (en) begin
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d1[(WIDTH-1):0] <= d2[(WIDTH-1):0];
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d2[(WIDTH-1):0] <= in[(WIDTH-1):0];
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end; // if
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end // else
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end
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wire [(WIDTH-1):0] switch_hi = (d2[(WIDTH-1):0] & d1[(WIDTH-1):0]);
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wire [(WIDTH-1):0] n_switch_lo = (d2[(WIDTH-1):0] | d1[(WIDTH-1):0]);
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SetReset SR (
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.clk(clk),
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.nrst(nrst),
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.s(switch_hi[(WIDTH-1):0]),
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.r(~n_switch_lo[(WIDTH-1):0]),
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.q(out[(WIDTH-1):0]),
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.nq()
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);
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defparam SR.WIDTH = WIDTH;
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endmodule |