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87 lines
2.8 KiB
Verilog
87 lines
2.8 KiB
Verilog
// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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//baeckler - 12-05-2007
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module clock_mux (clk,clk_select,clk_out);
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parameter NUM_CLOCKS = 4;
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parameter USE_FOLLOWERS = 1'b0;
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input [NUM_CLOCKS-1:0] clk;
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input [NUM_CLOCKS-1:0] clk_select; // one hot
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output clk_out;
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genvar i;
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reg [NUM_CLOCKS-1:0] ena_r0;
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reg [NUM_CLOCKS-1:0] ena_r1;
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reg [NUM_CLOCKS-1:0] ena_r2;
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wire [NUM_CLOCKS-1:0] qualified_sel;
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// A LUT can glitch when multiple inputs slew
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// simultaneously (in theory indepently of the function).
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// Insert a hard LCELL to prevent the unrelated clocks
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// from appearing on the same LUT.
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wire [NUM_CLOCKS-1:0] gated_clks /* synthesis keep */;
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initial begin
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ena_r0 = 0;
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ena_r1 = 0;
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ena_r2 = 0;
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end
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generate
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for (i=0; i<NUM_CLOCKS; i=i+1)
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begin : lp0
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wire [NUM_CLOCKS-1:0] tmp_mask;
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assign tmp_mask = {NUM_CLOCKS{1'b1}} ^ (1 << i);
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assign qualified_sel[i] = clk_select[i] &
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(~|(ena_r2 & tmp_mask));
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always @(posedge clk[i]) begin
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ena_r0[i] <= qualified_sel[i];
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ena_r1[i] <= ena_r0[i];
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end
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always @(negedge clk[i]) begin
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ena_r2[i] <= ena_r1[i];
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end
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if (USE_FOLLOWERS) begin
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wire cf_out;
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clock_follow cf (.clk_in(clk[i]),.clk_out(cf_out));
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assign gated_clks[i] = cf_out & ena_r2[i];
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end
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else begin
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assign gated_clks[i] = clk[i] & ena_r2[i];
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end
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end
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endgenerate
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// these will not exhibit simultaneous toggle by construction.
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assign clk_out = |gated_clks;
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endmodule |