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97 lines
3.3 KiB
Verilog
97 lines
3.3 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 3-20-2006
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// higher numbered select bits take priority over lower
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module priority_mux (sel,dat,out);
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parameter WIDTH = 24; // currently must be a multiple of 6
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localparam WIDTH_DIV_3 = WIDTH/3;
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localparam WIDTH_DIV_6 = WIDTH/6;
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input [WIDTH-1:0] sel;
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input [WIDTH-1:0] dat;
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output out;
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parameter METHOD = 1;
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genvar i;
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generate
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if (METHOD == 0) begin
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////////////////////////////////////////////
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// Generic
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////////////////////////////////////////////
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wire [WIDTH:0] partials;
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assign partials[0] = 1'b0;
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for (i=0; i<WIDTH; i=i+1)
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begin : m
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assign partials[i+1] = (!sel[i] & partials[i]) | (sel[i] & dat[i]);
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end
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assign out = partials[WIDTH];
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end
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else if (METHOD == 1) begin
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////////////////////////////////////////////
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// With some hard grouping for speed
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////////////////////////////////////////////
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// priority mux within a block of 6
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wire [WIDTH_DIV_3-1:0] triples /* synthesis keep */;
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for (i=0; i<WIDTH_DIV_3; i=i+1)
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begin : m3
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assign triples[i] = sel[3*i+2] ? dat[3*i+2] :
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sel[3*i+1] ? dat[3*i+1] :
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sel[3*i] ? dat[3*i] : 1'b0;
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end
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// aggregate the select signals to chunks of 6
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wire [WIDTH_DIV_6-1:0] grouped_select /* synthesis keep */;
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for (i=0; i<WIDTH_DIV_6; i=i+1)
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begin : sg
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assign grouped_select[i] = |sel[6*i+5:6*i];
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end
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// see if a block of 6 higher than mine is active
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wire [WIDTH_DIV_6-1:0] higher_select;
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for (i=0; i<WIDTH_DIV_6-1; i=i+1)
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begin : hs
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assign higher_select[i] = |grouped_select[WIDTH_DIV_6-1:i];
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end
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assign higher_select[WIDTH_DIV_6-1] = 1'b0;
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// priority mux within a block of 6
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// refer to the higher signal for between block
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// priority
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wire [WIDTH_DIV_6-1:0] sixes;
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for (i=0; i<WIDTH_DIV_6; i=i+1)
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begin : m6
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assign sixes[i] = !higher_select[i] & (
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triples[2*i+1] |
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(!sel[6*i+3] & !sel[6*i+4] & !sel[6*i+5] & triples[2*i]));
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end
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assign out = |sixes;
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end
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endgenerate
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endmodule
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