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120 lines
2.9 KiB
Verilog
120 lines
2.9 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module rgb_to_hue_tb ();
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reg clk,rst;
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reg [7:0] r,g,b;
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wire [7:0] h;
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rgb_to_hue r2h
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(
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.clk(clk),
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.rst(rst),
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.r(r),
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.g(g),
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.b(b),
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.hue(h)
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);
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integer n = 0;
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real error;
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reg [7:0] max3,min3;
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real delta,rdist,gdist,bdist,hue;
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real hue_d,hue_dd,hue_ddd,hue_dddd;
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initial begin
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clk = 0;
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rst = 1'b1;
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r=0;
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g=0;
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b=0;
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@(posedge clk);
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@(negedge clk);
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rst = 1'b0;
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@(negedge clk);
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for (n=0;n<1000000;n=n+1)
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begin
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@(negedge clk);
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r = $random; g = $random; b = $random;
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@(negedge clk);
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@(posedge clk);
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#1
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error = h - hue_ddd;
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if (error > 2 || error < -2) begin
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if (delta < 16) begin
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$display ("Marginal - Low delta value %f with error %f at time %d",
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delta,error,$time);
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end
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else begin
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$display ("Error - Outside of range at time %d",$time);
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#100
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$stop();
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end
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end
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end
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$display ("PASS");
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$stop();
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end
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always @(posedge clk) begin
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max3 = (r > g) ? ((r > b) ? r : b) :
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((g > b) ? g : b);
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min3 = (r < g) ? ((r < b) ? r : b) :
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((g < b) ? g : b);
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delta = max3 - min3;
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if (delta == 0) hue = 0;
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else begin
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rdist = (max3 - r) / delta;
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gdist = (max3 - g) / delta;
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bdist = (max3 - b) / delta;
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if (r == max3) begin
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hue = 40 * ((g/delta) - (b/delta));
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end
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else if (g == max3) begin
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hue = 80 + 40 * ((b/delta) - (r/delta));
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end
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else begin
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hue = 160 + 40 * ((r/delta) - (g/delta));
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end
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if (hue < 0) hue = hue + 240;
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if (hue >= 240) hue = hue - 240;
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end
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hue_d <= hue;
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hue_dd <= hue_d;
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hue_ddd <= hue_dd;
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hue_dddd <= hue_ddd;
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end
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always begin
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#100 clk = ~clk;
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end
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endmodule |