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Quartus benchmark project ========================= Konstantin Pavlov, pavlovconst@gmail.com This project uses dynamic_delay.sv module to model both high-register count and combinational-intensive design. See Quartus "Messages" tab for TOTAL time spent for compilation. This will give you some quantitive charachteristic of your environment processing power. You can also compare how different machines and environments deal with this typical design when compiling for FPGAs. I use only pure RTL code here with intention to leave an opportunity to compare compilation time across all possible IDE`s and even across all FPGA vendors.