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88 lines
1.8 KiB
Verilog
88 lines
1.8 KiB
Verilog
//------------------------------------------------------------------------------
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// main_tb.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Testbench template with basic clocking, reset and random stimulus signals
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// See main_tb.sv file for SystemVerilog version of this module
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`timescale 1ns / 1ps
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module main_tb();
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reg clk200;
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initial begin
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#0 clk200 = 1;
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forever
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#2.5 clk200 = ~clk200;
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end
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reg rst;
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initial begin
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#10.2 rst = 1;
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#5 rst = 0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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wire nrst = ~rst;
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reg rst_once;
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initial begin // initializing non-X data before PLL starts
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#10.2 rst_once = 1;
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#5 rst_once = 0;
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end
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initial begin
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#510.2 rst_once = 1; // PLL starts at 500ns, clock appears, so doing the reset for modules
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#5 rst_once = 0;
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end
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wire nrst_once = ~rst_once;
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wire [31:0] DerivedClocks;
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ClkDivider CD1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.out( DerivedClocks[31:0] )
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);
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defparam CD1.WIDTH = 32;
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wire [31:0] E_DerivedClocks;
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EdgeDetect ED1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.in( DerivedClocks[31:0] ),
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.rising( E_DerivedClocks[31:0] ),
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.falling( ),
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.both( )
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);
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defparam ED1.WIDTH = 32;
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wire [15:0] RandomNumber1;
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c_rand RNG1 (
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.clk( clk200 ),
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.rst( rst_once ),
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.reseed( 1'b0 ),
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.seed_val( DerivedClocks[31:0] ),
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.out( RandomNumber1[15:0] )
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);
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reg start;
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initial begin
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#100.2 start = 1;
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#5 start = 0;
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end
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// Module under test ==========================================================
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wire out1,out2;
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Main M ( // module under test
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clk200,~clk200,
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rst_once,
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out1,out2 // for compiler not to remove logic
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);
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endmodule
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