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82 lines
2.5 KiB
Verilog
82 lines
2.5 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 01-04-2007
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module pipeline_add_tb ();
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parameter LS_WIDTH = 15;
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parameter MS_WIDTH = 20;
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parameter WIDTH = LS_WIDTH + MS_WIDTH;
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reg [WIDTH-1:0] a,b;
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reg rst,clk;
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wire [WIDTH-1:0] oa;
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reg first = 1'b1;
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// functional model
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reg [WIDTH-1:0] ob,ob_delay;
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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ob_delay <= 0;
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ob <= 0;
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end
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else begin
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ob_delay <= ob;
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ob <= a + b;
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end
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end
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// DUT
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pipeline_add s (.clk(clk),.rst(rst),.a(a),.b(b),.o(oa));
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defparam s .LS_WIDTH = LS_WIDTH;
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defparam s .MS_WIDTH = MS_WIDTH;
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// run the clock and spin A and B data
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always begin
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#100 clk = ~clk;
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end
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always @(negedge clk) begin
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a = {$random,$random};
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b = {$random,$random};
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end
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// verify - ignore the very first tick while the
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// pipe clears.
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always @(posedge clk) begin
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#10 if (!first && oa !== ob_delay) begin
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$display ("Mismatch at time %d",$time);
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$stop();
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end
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end
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initial begin
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clk = 0;
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rst = 0;
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#10 rst = 1;
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#10 rst = 0;
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@(posedge clk)
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@(negedge clk) first = 0;
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#1000000 $display ("PASS");
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$stop();
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end
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endmodule |