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243 lines
6.0 KiB
Verilog
243 lines
6.0 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 04-07-2006
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// compare 8b10b encoder / decoders
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module encoder_tb ();
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reg fail ;
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reg clk;
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reg rst_n;
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reg kin_ena;
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reg ein_ena;
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reg [7:0] ein_dat;
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reg ein_rd;
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wire eout_val_a,eout_val_b;
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wire [9:0] eout_dat_a,eout_dat_b;
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wire eout_rdcomb_a,eout_rdcomb_b;
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wire eout_rdreg_a,eout_rdreg_b;
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wire valid,kerr;
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///////////////////////////////////
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// Encoder units
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///////////////////////////////////
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encoder_8b10b ea (
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.clk(clk),
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.rst(!rst_n),
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.kin_ena(kin_ena),
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.ein_ena(ein_ena),
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.ein_dat(ein_dat),
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.ein_rd(ein_rd),
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.eout_val(eout_val_a),
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.eout_dat(eout_dat_a),
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.eout_rdcomb(eout_rdcomb_a),
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.eout_rdreg(eout_rdreg_a)
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);
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defparam ea .METHOD = 0;
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encoder_8b10b eb (
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.clk(clk),
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.rst(!rst_n),
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.kin_ena(kin_ena),
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.ein_ena(ein_ena),
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.ein_dat(ein_dat),
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.ein_rd(ein_rd),
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.eout_val(eout_val_b),
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.eout_dat(eout_dat_b),
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.eout_rdcomb(eout_rdcomb_b),
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.eout_rdreg(eout_rdreg_b)
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);
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defparam eb .METHOD = 1;
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/////////////////////////////////////////
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//Lag some signals for decoder checking
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/////////////////////////////////////////
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reg [7:0] late_data;
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reg [7:0] late_late_data;
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reg late_ein_rd;
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always @(posedge clk) begin
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late_late_data <= late_data;
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late_data <= ein_dat;
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late_ein_rd <= ein_rd;
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end
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///////////////////////////////////
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// Decoder units
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///////////////////////////////////
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wire [7:0] dat_de,dat_df;
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wire kerr_de,kerr_df;
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wire rderr_de,rderr_df;
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wire k_de,k_df;
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wire rdreg_de,rdreg_df;
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// fake some errors
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reg inject_rd_error;
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reg [63:0] inject_k_error;
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decoder_8b10b de (
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.clk(clk),
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.rst(!rst_n),
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.din_ena(1'b1),
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.din_dat(eout_dat_a ^ inject_k_error[9:0]),
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.din_rd(late_ein_rd ^ inject_rd_error),
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.dout_val(),
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.dout_dat(dat_de),
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.dout_k(k_de),
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.dout_kerr(kerr_de),
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.dout_rderr(rderr_de),
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.dout_rdcomb(),
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.dout_rdreg(rdreg_de)
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);
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defparam de .METHOD = 0;
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decoder_8b10b df (
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.clk(clk),
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.rst(!rst_n),
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.din_ena(1'b1),
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.din_dat(eout_dat_a ^ inject_k_error[9:0]),
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.din_rd(late_ein_rd ^ inject_rd_error),
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.dout_val(),
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.dout_dat(dat_df),
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.dout_k(k_df),
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.dout_kerr(kerr_df),
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.dout_rderr(rderr_df),
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.dout_rdcomb(),
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.dout_rdreg(rdreg_df)
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);
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defparam df .METHOD = 1;
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initial begin
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clk = 0;
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rst_n = 1;
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kin_ena = 0;
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ein_ena = 0;
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ein_dat = 0;
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ein_rd = 0;
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fail = 0;
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inject_rd_error = 0;
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inject_k_error = 1;
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#10 rst_n = 0;
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#10 rst_n = 1;
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#2000000
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if (!fail) $display ("PASS");
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$stop();
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end
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always begin
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#100 clk = ~clk;
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end
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///////////////////////////////////////////
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// not all data for transmit is legal.
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///////////////////////////////////////////
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reg [3:0] tmp;
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always @(negedge clk or negedge rst_n) begin
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ein_ena = $random;
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kin_ena = !ein_ena;
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tmp = $random % 4'hd;
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if (kin_ena) begin
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case (tmp)
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// valid K signals
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4'h0 : ein_dat = 8'b000_11100;
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4'h1 : ein_dat = 8'b000_11100;
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4'h2 : ein_dat = 8'b001_11100;
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4'h3 : ein_dat = 8'b010_11100;
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4'h4 : ein_dat = 8'b011_11100;
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4'h5 : ein_dat = 8'b100_11100;
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4'h6 : ein_dat = 8'b101_11100;
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4'h7 : ein_dat = 8'b110_11100;
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4'h8 : ein_dat = 8'b111_11100;
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4'h9 : ein_dat = 8'b111_10111;
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4'ha : ein_dat = 8'b111_11011;
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4'hb : ein_dat = 8'b111_11101;
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4'hc : ein_dat = 8'b111_11110;
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// 4'hd : ein_dat = 8'b111_11111;
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default : ein_dat = 0;
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endcase
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end
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else
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ein_dat = $random;
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end
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// random inputs
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always @(negedge clk) begin
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// TX rd is completely random
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ein_rd = $random;
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// tell the RX the wrong RD sometimes, data
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// should be OK
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inject_rd_error = $random;
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inject_k_error = (inject_k_error << 1) | inject_k_error[63];
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end
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always @(posedge clk) begin
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#10
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///////////////////////////////////
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// compare encoders A and B
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///////////////////////////////////
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if (eout_val_a != eout_val_b ||
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eout_dat_a != eout_dat_b ||
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eout_rdcomb_a != eout_rdcomb_b ||
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eout_rdreg_a != eout_rdreg_b
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)
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begin
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$display ("Mismatch between A and B at time %d",$time);
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fail = 1;
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end
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///////////////////////////////////
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// compare decoder E to encoded data
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///////////////////////////////////
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if (dat_de != late_late_data) begin
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// make sure it isn't an error that was injected intentionally
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if (~|inject_k_error[10:0]) begin
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$display ("Decoded data mismatch at time %d",$time);
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fail = 1;
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end
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end
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///////////////////////////////////
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// compare decoders E and F
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///////////////////////////////////
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if (dat_de != dat_df ||
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kerr_de != kerr_df ||
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rderr_de != rderr_df ||
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k_de != k_df ||
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rdreg_de != rdreg_df)
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begin
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$display ("Mismatch between E and F at time %d",$time);
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fail = 1;
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end
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end
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endmodule |