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83 lines
2.5 KiB
Verilog
83 lines
2.5 KiB
Verilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 01-09-2008
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module gearbox_33_32 (
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input clk,arst,
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input [32:0] din,
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input din_valid,
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output din_ready,
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output [31:0] dout,
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output reg dout_valid,
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input dout_ready
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);
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reg [4:0] holding;
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reg holding_32;
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reg [63:0] storage;
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assign din_ready = dout_ready & !holding_32;
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// holding will never be >= 32
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wire [63:0] aligned_din = (din << holding);
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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storage <= 0;
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holding <= 0;
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holding_32 <= 0;
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dout_valid <= 1'b0;
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end
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else begin
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if (dout_ready) dout_valid <= 1'b0;
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if (holding_32) begin
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holding <= 0;
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holding_32 <= 0;
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storage <= (storage >> 32);
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dout_valid <= 1'b1;
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end
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else begin
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if (din_ready & din_valid) begin
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storage <= (storage >> 32) | aligned_din;
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// when holding 31, 33 in, there are enough
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// bits for TWO words out.
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if (&holding) begin
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holding <= 0;
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holding_32 <= 1'b1;
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end
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else begin
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holding <= holding + 1'b1;
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end
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dout_valid <= 1'b1;
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end
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end
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end
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end
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assign dout = storage [31:0];
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endmodule |