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125 lines
3.6 KiB
Verilog
125 lines
3.6 KiB
Verilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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// baeckler - 09-19-2008
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module word_align_control (
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input clk, arst,
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input din_framed,
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input din_valid,
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output reg slip_to_frame,
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output reg word_locked
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);
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////////////////////////////////
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// count mis-framed din words
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// stop counting at 16
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/////////////////////////////////
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reg rst_sync_err_cntr;
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reg [4:0] sync_err_cntr;
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always @(posedge clk or posedge arst) begin
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if (arst) sync_err_cntr <= 0;
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else begin
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if (rst_sync_err_cntr) sync_err_cntr <= 0;
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else if (din_valid & !din_framed & !sync_err_cntr[4])
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sync_err_cntr <= sync_err_cntr + 1'b1;
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end
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end
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/////////////////////////////////
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// count words, modulus 64
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/////////////////////////////////
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reg rst_word_cntr;
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reg [5:0] word_cntr;
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reg word_cntr_max;
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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word_cntr <= 0;
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word_cntr_max <= 1'b0;
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end
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else begin
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if (rst_word_cntr) begin
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word_cntr <= 0;
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word_cntr_max <= 1'b0;
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end
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else if (din_valid) begin
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word_cntr <= word_cntr + 1'b1;
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word_cntr_max <= (word_cntr == 6'b111110);
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end
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end
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end
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/////////////////////////////////
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// Little control machine
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// implementing figure 5-10 from Interlaken 1.1 spec
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/////////////////////////////////
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localparam ST_RESET = 2'h0,
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ST_SLIP = 2'h1,
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ST_VERIFY = 2'h2,
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ST_LOCKED = 2'h3;
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reg [1:0] state, next_state;
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always @(*) begin
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next_state = state;
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slip_to_frame = 1'b0;
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rst_word_cntr = 1'b0;
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rst_sync_err_cntr = 1'b0;
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word_locked = 1'b0;
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case (state)
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ST_RESET: begin
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next_state = ST_SLIP;
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end
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ST_SLIP: begin
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slip_to_frame = 1'b1;
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rst_word_cntr = 1'b1;
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if (din_valid & din_framed) next_state = ST_VERIFY;
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end
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ST_VERIFY: begin
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// On any error return to slipping
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// On 64 successful tests goto locked
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if (din_valid & !din_framed) next_state = ST_SLIP;
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else if (word_cntr_max) next_state = ST_LOCKED;
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end
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ST_LOCKED: begin
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// Look for 16 or more bad syncs in a
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// 64 word window to indicate loss of lock
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word_locked = 1'b1;
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if (word_cntr_max) begin
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rst_sync_err_cntr = 1'b1;
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if (sync_err_cntr[4]) begin
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// lost it.
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next_state = ST_SLIP;
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end
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end
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end
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endcase
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end
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always @(posedge clk or posedge arst) begin
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if (arst) state <= ST_RESET;
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else state <= next_state;
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end
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endmodule |