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95 lines
2.9 KiB
Verilog
95 lines
2.9 KiB
Verilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 12-17-2008
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// Order:
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// given 76543210, fedcba98, nmlkjihg
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// output jihg fedcba98 76543210 as the first word
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module eight_to_twenty #(
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parameter WORD_LEN = 66
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)
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(
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input clk,arst,
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input [8*WORD_LEN-1:0] din,
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input din_valid,
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output din_ready,
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output reg [20*WORD_LEN-1:0] dout,
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input dout_ready,
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output reg dout_valid
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);
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// Possible states :
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// 0 : 20 out, no residue
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// 1 : holding 8 words
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// 2 : holding 16 words
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// 3 : 20 out, holding residue of 4
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// 4 : holding 12 words
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reg [4:0] state;
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wire input_wait = din_ready & !din_valid;
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wire output_wait = dout_valid & !dout_ready;
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assign din_ready = !output_wait;
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always @(posedge clk or posedge arst) begin
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if (arst) state <= 5'b1;
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else if (!input_wait & !output_wait)
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state <= {state [3:0],state[4]};
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end
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reg [4*WORD_LEN-1:0] surplus;
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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dout <= 0;
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dout_valid <= 0;
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end
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else begin
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if (!input_wait & !output_wait) begin
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if (state[0]) begin
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dout[8*WORD_LEN-1:0] <= din;
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end
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if (state[1]) begin
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dout[16*WORD_LEN-1:8*WORD_LEN] <= din;
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end
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if (state[2]) begin
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dout[20*WORD_LEN-1:16*WORD_LEN] <= din[4*WORD_LEN-1:0];
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surplus <= din[8*WORD_LEN-1:4*WORD_LEN];
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dout_valid <= 1'b1;
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end
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if (state[3]) begin
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dout[4*WORD_LEN-1:0] <= surplus;
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dout[12*WORD_LEN-1:4*WORD_LEN] <= din;
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end
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if (state[4]) begin
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dout[20*WORD_LEN-1:12*WORD_LEN] <= din;
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dout_valid <= 1'b1;
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end
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end
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if (dout_valid & dout_ready) dout_valid <= 1'b0;
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end
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end
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endmodule
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