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253 lines
8.1 KiB
Verilog
253 lines
8.1 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 04-24-2007
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module simple_quad (
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clk,
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wraddr_a,wraddr_b,
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wrdat_a, wrdat_b,
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we_a, we_b,
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rdaddr_a,rdaddr_b,
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rddat_a,rddat_b
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);
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parameter ADDR_WIDTH = 5;
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parameter NUM_WORDS = 1 << ADDR_WIDTH;
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parameter DATA_WIDTH = 32;
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input clk;
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input [ADDR_WIDTH-1:0] wraddr_a,wraddr_b,rdaddr_a,rdaddr_b;
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input [DATA_WIDTH-1:0] wrdat_a,wrdat_b;
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input we_a,we_b;
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output [DATA_WIDTH-1:0] rddat_a,rddat_b;
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flag_array fa (
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.clk(clk),
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.waddr_a(wraddr_a),
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.waddr_b(wraddr_b),
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.we_a(we_a),
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.we_b(we_b),
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.raddr_a(rdaddr_a),
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.raddr_b(rdaddr_b),
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.sel_a(sel_a),
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.sel_b(sel_b)
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);
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defparam fa .ADDR_WIDTH = ADDR_WIDTH;
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//
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// Bank Q - Write A read A
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wire [DATA_WIDTH-1:0] rddata_q;
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altsyncram bank_q (
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.wren_a (we_a),
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.clock0 (clk),
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.address_a (wraddr_a),
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.address_b (rdaddr_a),
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.data_a (wrdat_a),
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.q_b (rddata_q),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({DATA_WIDTH{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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bank_q.address_reg_b = "CLOCK0",
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bank_q.clock_enable_input_a = "BYPASS",
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bank_q.clock_enable_input_b = "BYPASS",
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bank_q.clock_enable_output_a = "BYPASS",
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bank_q.clock_enable_output_b = "BYPASS",
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bank_q.intended_device_family = "Stratix II",
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bank_q.lpm_type = "altsyncram",
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bank_q.numwords_a = NUM_WORDS,
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bank_q.numwords_b = NUM_WORDS,
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bank_q.operation_mode = "DUAL_PORT",
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bank_q.outdata_aclr_b = "NONE",
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bank_q.outdata_reg_b = "CLOCK0",
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bank_q.power_up_uninitialized = "FALSE",
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bank_q.read_during_write_mode_mixed_ports = "DONT_CARE",
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bank_q.widthad_a = ADDR_WIDTH,
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bank_q.widthad_b = ADDR_WIDTH,
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bank_q.width_a = DATA_WIDTH,
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bank_q.width_b = DATA_WIDTH,
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bank_q.width_byteena_a = 1;
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//
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// Bank R - Write A read B
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wire [DATA_WIDTH-1:0] rddata_r;
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altsyncram bank_r (
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.wren_a (we_a),
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.clock0 (clk),
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.address_a (wraddr_a),
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.address_b (rdaddr_b),
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.data_a (wrdat_a),
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.q_b (rddata_r),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({DATA_WIDTH{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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bank_r.address_reg_b = "CLOCK0",
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bank_r.clock_enable_input_a = "BYPASS",
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bank_r.clock_enable_input_b = "BYPASS",
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bank_r.clock_enable_output_a = "BYPASS",
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bank_r.clock_enable_output_b = "BYPASS",
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bank_r.intended_device_family = "Stratix II",
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bank_r.lpm_type = "altsyncram",
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bank_r.numwords_a = NUM_WORDS,
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bank_r.numwords_b = NUM_WORDS,
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bank_r.operation_mode = "DUAL_PORT",
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bank_r.outdata_aclr_b = "NONE",
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bank_r.outdata_reg_b = "CLOCK0",
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bank_r.power_up_uninitialized = "FALSE",
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bank_r.read_during_write_mode_mixed_ports = "DONT_CARE",
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bank_r.widthad_a = ADDR_WIDTH,
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bank_r.widthad_b = ADDR_WIDTH,
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bank_r.width_a = DATA_WIDTH,
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bank_r.width_b = DATA_WIDTH,
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bank_r.width_byteena_a = 1;
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//
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// Bank S - Write B read A
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wire [DATA_WIDTH-1:0] rddata_s;
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altsyncram bank_s (
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.wren_a (we_b),
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.clock0 (clk),
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.address_a (wraddr_b),
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.address_b (rdaddr_a),
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.data_a (wrdat_b),
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.q_b (rddata_s),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({DATA_WIDTH{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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bank_s.address_reg_b = "CLOCK0",
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bank_s.clock_enable_input_a = "BYPASS",
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bank_s.clock_enable_input_b = "BYPASS",
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bank_s.clock_enable_output_a = "BYPASS",
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bank_s.clock_enable_output_b = "BYPASS",
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bank_s.intended_device_family = "Stratix II",
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bank_s.lpm_type = "altsyncram",
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bank_s.numwords_a = NUM_WORDS,
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bank_s.numwords_b = NUM_WORDS,
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bank_s.operation_mode = "DUAL_PORT",
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bank_s.outdata_aclr_b = "NONE",
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bank_s.outdata_reg_b = "CLOCK0",
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bank_s.power_up_uninitialized = "FALSE",
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bank_s.read_during_write_mode_mixed_ports = "DONT_CARE",
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bank_s.widthad_a = ADDR_WIDTH,
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bank_s.widthad_b = ADDR_WIDTH,
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bank_s.width_a = DATA_WIDTH,
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bank_s.width_b = DATA_WIDTH,
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bank_s.width_byteena_a = 1;
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//
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// Bank T - Write B read B
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wire [DATA_WIDTH-1:0] rddata_t;
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altsyncram bank_t (
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.wren_a (we_b),
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.clock0 (clk),
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.address_a (wraddr_b),
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.address_b (rdaddr_b),
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.data_a (wrdat_b),
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.q_b (rddata_t),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({DATA_WIDTH{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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bank_t.address_reg_b = "CLOCK0",
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bank_t.clock_enable_input_a = "BYPASS",
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bank_t.clock_enable_input_b = "BYPASS",
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bank_t.clock_enable_output_a = "BYPASS",
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bank_t.clock_enable_output_b = "BYPASS",
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bank_t.intended_device_family = "Stratix II",
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bank_t.lpm_type = "altsyncram",
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bank_t.numwords_a = NUM_WORDS,
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bank_t.numwords_b = NUM_WORDS,
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bank_t.operation_mode = "DUAL_PORT",
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bank_t.outdata_aclr_b = "NONE",
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bank_t.outdata_reg_b = "CLOCK0",
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bank_t.power_up_uninitialized = "FALSE",
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bank_t.read_during_write_mode_mixed_ports = "DONT_CARE",
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bank_t.widthad_a = ADDR_WIDTH,
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bank_t.widthad_b = ADDR_WIDTH,
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bank_t.width_a = DATA_WIDTH,
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bank_t.width_b = DATA_WIDTH,
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bank_t.width_byteena_a = 1;
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assign rddat_a = sel_a ? rddata_s : rddata_q;
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assign rddat_b = sel_b ? rddata_t : rddata_r;
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endmodule |