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basic_verilog/example_projects/testbench_template_tb
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Konstantin Pavlov 0d9f67ff80 Updated testbench template
2022-07-03 16:39:54 +03:00
..
.gitignore
Added testbench template
2021-11-01 14:47:08 +03:00
clean_modelsim.bat
Updated scripts
2022-06-06 09:52:10 +03:00
clk_divider.sv
Added testbench template
2021-11-01 14:47:08 +03:00
compile.bat
Added testbench template
2021-11-01 14:47:08 +03:00
compile.tcl
Updated tb template with clock gen module
2022-06-19 20:18:37 +03:00
delay.sv
Added testbench template
2021-11-01 14:47:08 +03:00
edge_detect.sv
Added Fmax computation script for Xilinx Vivado
2022-05-01 15:01:47 +03:00
main_tb.sv
Updated testbench template
2022-07-03 16:39:54 +03:00
sim_clk_gen.sv
Updated tb template with clock gen module
2022-06-19 20:18:37 +03:00