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127 lines
3.1 KiB
Verilog
127 lines
3.1 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 07-05-2006
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////////////////////////////////////////////
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// Quick test bench
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////////////////////////////////////////////
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module gray_cntr_tb ();
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parameter WIDTH = 20;
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reg clk, rst, ena, sclr;
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wire [WIDTH-1:0] q,b,c;
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reg fail;
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gray_cntr cntrc (
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.clk(clk),
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.rst(rst),
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.ena(ena),
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.sclr(sclr),
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.q(q)
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);
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defparam cntrc .WIDTH = WIDTH;
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gray_cntr_la cntrla (
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.clk(clk),
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.rst(rst),
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.ena(ena),
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.sclr(sclr),
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.q(b)
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);
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defparam cntrla .WIDTH = WIDTH;
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defparam cntrla .METHOD = 0;
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gray_cntr_la cntrlac (
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.clk(clk),
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.rst(rst),
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.ena(ena),
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.sclr(sclr),
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.q(c)
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);
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defparam cntrlac .WIDTH = WIDTH;
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defparam cntrlac .METHOD = 1;
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// Reference unit
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reg [WIDTH-1:0] backup_q;
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always @(posedge clk or posedge rst) begin
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if (rst) backup_q <= 0;
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else if (ena) begin
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if (sclr) backup_q <= 0;
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else backup_q <= backup_q + 1'b1;
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end
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end
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reg allow_sclr;
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initial begin
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clk = 0;
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rst = 0;
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ena = 1;
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sclr = 0;
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fail = 0;
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allow_sclr = 0;
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#10 rst = 1;
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#10 rst = 0;
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@(&backup_q) #10000 if (!fail) $display ("Count to max pass");
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@(negedge clk) allow_sclr = 1;
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#1000000
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@(negedge clk);
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if (!fail) $display ("Random SCLR pass");
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allow_sclr = 0;
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if (!fail) $display ("PASS");
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$stop();
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end
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always begin
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#100 clk = ~clk;
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end
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always @(negedge clk) begin
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if ((backup_q ^ (backup_q >> 1)) !== q) begin
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$display ("Q Mismatch time at %d",$time);
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fail = 1;
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end
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if ((backup_q ^ (backup_q >> 1)) !== b) begin
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$display ("B Mismatch time at %d",$time);
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fail = 1;
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end
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if ((backup_q ^ (backup_q >> 1)) !== c) begin
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$display ("C Mismatch time at %d",$time);
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fail = 1;
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end
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ena = $random | $random;
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sclr = allow_sclr & (($random % 100) == 0) ;
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#10 if (fail) #1000 $stop();
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end
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endmodule
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