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https://github.com/pConst/basic_verilog.git
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301 lines
10 KiB
Verilog
301 lines
10 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 12-15-2006
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// pipelined Rijndael / AES256 encrypt and decrypt units
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////////////////////////////////////
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// Encrypt using 256 bit key
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////////////////////////////////////
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module aes_256 (clk,clr,dat_in,dat_out,key,inv_key);
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input clk,clr;
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input [127:0] dat_in;
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input [255:0] key;
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output [127:0] dat_out;
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output [255:0] inv_key;
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parameter LATENCY = 14; // currently allowed 0,14
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localparam ROUND_LATENCY = (LATENCY == 14 ? 1 : 0);
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wire [127:0] start1,start2,start3,start4,start5;
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wire [127:0] start6,start7,start8,start9,start10;
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wire [127:0] start11,start12,start13,start14;
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wire [255:0] key1,key2,key3,key4,key5;
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wire [255:0] key6,key7,key8,key9,key10;
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wire [255:0] key11,key12,key13,key14;
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assign start1 = dat_in ^ key[255:128];
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assign key1 = key;
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aes_round_256 r1 (
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.clk(clk),.clr(clr),
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.dat_in(start1),.key_in(key1),
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.dat_out(start2),.key_out(key2),
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.skip_mix_col(1'b0),
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.rconst(8'h01));
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defparam r1 .LATENCY = ROUND_LATENCY;
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defparam r1 .KEY_EVOLVE_TYPE = 0;
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aes_round_256 r2 (
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.clk(clk),.clr(clr),
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.dat_in(start2),.key_in(key2),
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.dat_out(start3),.key_out(key3),
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.skip_mix_col(1'b0),
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.rconst(8'h01));
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defparam r2 .LATENCY = ROUND_LATENCY;
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defparam r2 .KEY_EVOLVE_TYPE = 1;
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aes_round_256 r3 (
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.clk(clk),.clr(clr),
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.dat_in(start3),.key_in(key3),
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.dat_out(start4),.key_out(key4),
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.skip_mix_col(1'b0),
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.rconst(8'h02));
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defparam r3 .LATENCY = ROUND_LATENCY;
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defparam r3 .KEY_EVOLVE_TYPE = 0;
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aes_round_256 r4 (
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.clk(clk),.clr(clr),
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.dat_in(start4),.key_in(key4),
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.dat_out(start5),.key_out(key5),
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.skip_mix_col(1'b0),
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.rconst(8'h02));
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defparam r4 .LATENCY = ROUND_LATENCY;
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defparam r4 .KEY_EVOLVE_TYPE = 1;
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aes_round_256 r5 (
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.clk(clk),.clr(clr),
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.dat_in(start5),.key_in(key5),
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.dat_out(start6),.key_out(key6),
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.skip_mix_col(1'b0),
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.rconst(8'h04));
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defparam r5 .LATENCY = ROUND_LATENCY;
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defparam r5 .KEY_EVOLVE_TYPE = 0;
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aes_round_256 r6 (
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.clk(clk),.clr(clr),
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.dat_in(start6),.key_in(key6),
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.dat_out(start7),.key_out(key7),
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.skip_mix_col(1'b0),
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.rconst(8'h04));
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defparam r6 .LATENCY = ROUND_LATENCY;
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defparam r6 .KEY_EVOLVE_TYPE = 1;
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aes_round_256 r7 (
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.clk(clk),.clr(clr),
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.dat_in(start7),.key_in(key7),
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.dat_out(start8),.key_out(key8),
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.skip_mix_col(1'b0),
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.rconst(8'h08));
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defparam r7 .LATENCY = ROUND_LATENCY;
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defparam r7 .KEY_EVOLVE_TYPE = 0;
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aes_round_256 r8 (
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.clk(clk),.clr(clr),
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.dat_in(start8),.key_in(key8),
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.dat_out(start9),.key_out(key9),
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.skip_mix_col(1'b0),
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.rconst(8'h08));
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defparam r8 .LATENCY = ROUND_LATENCY;
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defparam r8 .KEY_EVOLVE_TYPE = 1;
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aes_round_256 r9 (
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.clk(clk),.clr(clr),
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.dat_in(start9),.key_in(key9),
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.dat_out(start10),.key_out(key10),
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.skip_mix_col(1'b0),
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.rconst(8'h10));
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defparam r9 .LATENCY = ROUND_LATENCY;
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defparam r9 .KEY_EVOLVE_TYPE = 0;
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aes_round_256 r10 (
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.clk(clk),.clr(clr),
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.dat_in(start10),.key_in(key10),
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.dat_out(start11),.key_out(key11),
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.skip_mix_col(1'b0),
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.rconst(8'h10));
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defparam r10 .LATENCY = ROUND_LATENCY;
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defparam r10 .KEY_EVOLVE_TYPE = 1;
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aes_round_256 r11 (
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.clk(clk),.clr(clr),
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.dat_in(start11),.key_in(key11),
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.dat_out(start12),.key_out(key12),
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.skip_mix_col(1'b0),
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.rconst(8'h20));
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defparam r11 .LATENCY = ROUND_LATENCY;
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defparam r11 .KEY_EVOLVE_TYPE = 0;
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aes_round_256 r12 (
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.clk(clk),.clr(clr),
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.dat_in(start12),.key_in(key12),
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.dat_out(start13),.key_out(key13),
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.skip_mix_col(1'b0),
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.rconst(8'h20));
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defparam r12 .LATENCY = ROUND_LATENCY;
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defparam r12 .KEY_EVOLVE_TYPE = 1;
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aes_round_256 r13 (
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.clk(clk),.clr(clr),
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.dat_in(start13),.key_in(key13),
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.dat_out(start14),.key_out(key14),
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.skip_mix_col(1'b0),
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.rconst(8'h40));
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defparam r13 .LATENCY = ROUND_LATENCY;
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defparam r13 .KEY_EVOLVE_TYPE = 0;
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aes_round_256 r14 (
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.clk(clk),.clr(clr),
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.dat_in(start14),.key_in(key14),
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.dat_out(dat_out),.key_out(inv_key),
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.skip_mix_col(1'b1),
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.rconst(8'h40));
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defparam r14 .LATENCY = ROUND_LATENCY;
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defparam r14 .KEY_EVOLVE_TYPE = 1;
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endmodule
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////////////////////////////////////
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// Inverse (Decrypt) using 256 bit key
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////////////////////////////////////
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module inv_aes_256 (clk,clr,dat_in,dat_out,inv_key);
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input clk,clr;
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input [127:0] dat_in;
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input [255:0] inv_key;
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output [127:0] dat_out;
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parameter LATENCY = 14; // currently allowed 0,14
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localparam ROUND_LATENCY = (LATENCY == 14 ? 1 : 0);
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wire [127:0] start1,start2,start3,start4,start5;
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wire [127:0] start6,start7,start8,start9,start10;
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wire [127:0] start11,start12,start13,start14;
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wire [127:0] unkeyd_out;
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wire [255:0] last_key;
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wire [255:0] key1,key2,key3,key4,key5;
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wire [255:0] key6,key7,key8,key9,key10;
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wire [255:0] key11,key12,key13,key14;
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assign start1 = dat_in;
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assign key1 = inv_key;
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inv_aes_round_256 r1 (
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.clk(clk),.clr(clr),
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.dat_in(start1),.key_in(key1),
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.dat_out(start2),.key_out(key2),
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.skip_mix_col(1'b1),
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.rconst(8'h40));
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defparam r1 .LATENCY = ROUND_LATENCY;
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defparam r1 .KEY_EVOLVE_TYPE = 1;
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inv_aes_round_256 r2 (
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.clk(clk),.clr(clr),
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.dat_in(start2),.key_in(key2),
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.dat_out(start3),.key_out(key3),
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.skip_mix_col(1'b0),
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.rconst(8'h40));
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defparam r2 .LATENCY = ROUND_LATENCY;
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defparam r2 .KEY_EVOLVE_TYPE = 0;
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inv_aes_round_256 r3 (
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.clk(clk),.clr(clr),
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.dat_in(start3),.key_in(key3),
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.dat_out(start4),.key_out(key4),
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.skip_mix_col(1'b0),
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.rconst(8'h20));
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defparam r3 .LATENCY = ROUND_LATENCY;
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defparam r3 .KEY_EVOLVE_TYPE = 1;
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inv_aes_round_256 r4 (
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.clk(clk),.clr(clr),
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.dat_in(start4),.key_in(key4),
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.dat_out(start5),.key_out(key5),
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.skip_mix_col(1'b0),
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.rconst(8'h20));
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defparam r4 .LATENCY = ROUND_LATENCY;
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defparam r4 .KEY_EVOLVE_TYPE = 0;
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inv_aes_round_256 r5 (
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.clk(clk),.clr(clr),
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.dat_in(start5),.key_in(key5),
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.dat_out(start6),.key_out(key6),
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.skip_mix_col(1'b0),
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.rconst(8'h10));
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defparam r5 .LATENCY = ROUND_LATENCY;
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defparam r5 .KEY_EVOLVE_TYPE = 1;
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inv_aes_round_256 r6 (
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.clk(clk),.clr(clr),
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.dat_in(start6),.key_in(key6),
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.dat_out(start7),.key_out(key7),
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.skip_mix_col(1'b0),
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.rconst(8'h10));
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defparam r6 .LATENCY = ROUND_LATENCY;
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defparam r6 .KEY_EVOLVE_TYPE = 0;
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inv_aes_round_256 r7 (
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.clk(clk),.clr(clr),
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.dat_in(start7),.key_in(key7),
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.dat_out(start8),.key_out(key8),
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.skip_mix_col(1'b0),
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.rconst(8'h08));
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defparam r7 .LATENCY = ROUND_LATENCY;
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defparam r7 .KEY_EVOLVE_TYPE = 1;
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inv_aes_round_256 r8 (
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.clk(clk),.clr(clr),
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.dat_in(start8),.key_in(key8),
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.dat_out(start9),.key_out(key9),
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.skip_mix_col(1'b0),
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.rconst(8'h08));
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defparam r8 .LATENCY = ROUND_LATENCY;
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defparam r8 .KEY_EVOLVE_TYPE = 0;
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inv_aes_round_256 r9 (
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.clk(clk),.clr(clr),
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.dat_in(start9),.key_in(key9),
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.dat_out(start10),.key_out(key10),
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.skip_mix_col(1'b0),
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.rconst(8'h04));
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defparam r9 .LATENCY = ROUND_LATENCY;
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defparam r9 .KEY_EVOLVE_TYPE = 1;
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inv_aes_round_256 r10 (
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.clk(clk),.clr(clr),
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.dat_in(start10),.key_in(key10),
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.dat_out(start11),.key_out(key11),
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.skip_mix_col(1'b0),
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.rconst(8'h04));
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defparam r10 .LATENCY = ROUND_LATENCY;
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defparam r10 .KEY_EVOLVE_TYPE = 0;
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inv_aes_round_256 r11 (
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.clk(clk),.clr(clr),
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.dat_in(start11),.key_in(key11),
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.dat_out(start12),.key_out(key12),
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.skip_mix_col(1'b0),
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.rconst(8'h02));
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defparam r11 .LATENCY = ROUND_LATENCY;
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defparam r11 .KEY_EVOLVE_TYPE = 1;
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inv_aes_round_256 r12 (
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.clk(clk),.clr(clr),
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.dat_in(start12),.key_in(key12),
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.dat_out(start13),.key_out(key13),
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.skip_mix_col(1'b0),
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.rconst(8'h02));
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defparam r12 .LATENCY = ROUND_LATENCY;
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defparam r12 .KEY_EVOLVE_TYPE = 0;
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inv_aes_round_256 r13 (
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.clk(clk),.clr(clr),
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.dat_in(start13),.key_in(key13),
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.dat_out(start14),.key_out(key14),
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.skip_mix_col(1'b0),
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.rconst(8'h01));
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defparam r13 .LATENCY = ROUND_LATENCY;
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defparam r13 .KEY_EVOLVE_TYPE = 1;
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inv_aes_round_256 r14 (
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.clk(clk),.clr(clr),
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.dat_in(start14),.key_in(key14),
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.dat_out(unkeyd_out),.key_out(last_key),
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.skip_mix_col(1'b0),
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.rconst(8'h01));
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defparam r14 .LATENCY = ROUND_LATENCY;
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defparam r14 .KEY_EVOLVE_TYPE = 0;
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assign dat_out = last_key[255:128] ^ unkeyd_out;
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endmodule
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