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136 lines
4.2 KiB
Verilog
136 lines
4.2 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 03-08-2006
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/////////////////////////////////////////////////////////
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// one round of ENcipher and key evolve - 128 bit key
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/////////////////////////////////////////////////////////
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module aes_round_128 (
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clk,clr,dat_in,dat_out,rconst,skip_mix_col,key_in,key_out
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);
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input clk,clr;
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input [127:0] dat_in,key_in;
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input [7:0] rconst; // lower 24 bits are 0
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input skip_mix_col; // for the final round
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output [127:0] dat_out,key_out;
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parameter LATENCY = 0; // currently allowable values are 0,1
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reg [127:0] dat_out,key_out;
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// internal temp vars
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wire [127:0] dat_out_i,key_out_i,sub,shft,mix;
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reg [127:0] shft_r;
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// evolve key
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evolve_key_128 ek (.key_in(key_in),
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.rconst(rconst),.key_out(key_out_i));
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// first two LUT levels of work
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sub_bytes sb (.in(dat_in),.out(sub));
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shift_rows sr (.in(sub),.out(shft));
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// mid layer registers would go here, the keying
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// is awkward
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always @(shft) shft_r = shft;
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// second 2 LUT levels of work
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mix_columns mx (.in(shft_r),.out(mix));
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assign dat_out_i = (skip_mix_col ? shft : mix) ^ key_out_i;
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// conditional output register
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generate
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if (LATENCY!=0) begin
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always @(posedge clk or posedge clr) begin
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if (clr) dat_out <= 128'b0;
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else dat_out <= dat_out_i;
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end
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always @(posedge clk or posedge clr) begin
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if (clr) key_out <= 128'b0;
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else key_out <= key_out_i;
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end
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end
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else begin
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always @(dat_out_i) dat_out = dat_out_i;
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always @(key_out_i) key_out = key_out_i;
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end
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endgenerate
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endmodule
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/////////////////////////////////////////////////////////
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// one round of DEcipher and key evolve - 128 bit key
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/////////////////////////////////////////////////////////
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module inv_aes_round_128 (
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clk,clr,dat_in,dat_out,rconst,skip_mix_col,key_in,key_out
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);
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input clk,clr;
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input [127:0] dat_in,key_in;
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input [7:0] rconst; // lower 24 bits are 0
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input skip_mix_col; // for the final round
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output [127:0] dat_out,key_out;
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parameter LATENCY = 0; // currently allowable values are 0,1
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reg [127:0] dat_out,key_out;
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// internal temp vars
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wire [127:0] keyd_dat,dat_out_i,key_out_i,mixed,middle,shft;
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// inverse evolve key (for the next round)
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inv_evolve_key_128 ek (.key_in(key_in),
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.rconst(rconst),.key_out(key_out_i));
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// key the input data
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assign keyd_dat = dat_in ^ key_in;
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// optional skip of the mix columns step
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inv_mix_columns mx (.in(keyd_dat),.out(mixed));
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assign middle = (skip_mix_col ? keyd_dat : mixed);
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// second 2 levels of work
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inv_shift_rows sr (.in(middle),.out(shft));
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inv_sub_bytes sb (.in(shft),.out(dat_out_i));
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// conditional output register
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generate
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if (LATENCY!=0) begin
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always @(posedge clk or posedge clr) begin
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if (clr) dat_out <= 128'b0;
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else dat_out <= dat_out_i;
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end
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always @(posedge clk or posedge clr) begin
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if (clr) key_out <= 128'b0;
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else key_out <= key_out_i;
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end
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end
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else begin
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always @(dat_out_i) dat_out = dat_out_i;
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always @(key_out_i) key_out = key_out_i;
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end
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endgenerate
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endmodule
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