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69 lines
2.2 KiB
Verilog
69 lines
2.2 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 03-07-2006
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// the state
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// (msb) A B C D E F G H I J K L M N O P (lsb)
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//
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// shown as a grid :
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//
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// AEIM
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// BFJN
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// CGKO
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// DHLP
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//
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// Needs to be shifted to produce :
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//
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// AEIM
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// FJNB
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// KOCG
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// PDHL
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//
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module shift_rows (in,out);
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input [16*8-1 : 0] in;
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output [16*8-1 : 0] out;
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wire [16*8-1 : 0] out;
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assign out = {
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in[127:120],in[87:80],in[47:40],in[7:0],
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in[95:88],in[55:48],in[15:8],in[103:96],
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in[63:56],in[23:16],in[111:104],in[71:64],
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in[31:24],in[119:112],in[79:72],in[39:32] };
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endmodule
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module inv_shift_rows (in,out);
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input [16*8-1 : 0] in;
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output [16*8-1 : 0] out;
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wire [16*8-1 : 0] out;
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assign out = {
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in[127:120],in[23:16],in[47:40],in[71:64],
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in[95:88],in[119:112],in[15:8],in[39:32],
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in[63:56],in[87:80],in[111:104],in[7:0],
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in[31:24],in[55:48],in[79:72],in[103:96] };
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endmodule
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