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649 lines
12 KiB
Verilog
649 lines
12 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 1-19-2006
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module sbox0 (in,out);
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input [5:0] in;
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output [3:0] out;
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reg [3:0] out;
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always @(in) begin
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case (in)
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0 : out = 14;
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1 : out = 0;
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2 : out = 4;
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3 : out = 15;
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4 : out = 13;
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5 : out = 7;
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6 : out = 1;
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7 : out = 4;
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8 : out = 2;
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9 : out = 14;
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10 : out = 15;
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11 : out = 2;
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12 : out = 11;
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13 : out = 13;
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14 : out = 8;
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15 : out = 1;
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16 : out = 3;
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17 : out = 10;
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18 : out = 10;
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19 : out = 6;
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20 : out = 6;
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21 : out = 12;
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22 : out = 12;
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23 : out = 11;
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24 : out = 5;
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25 : out = 9;
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26 : out = 9;
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27 : out = 5;
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28 : out = 0;
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29 : out = 3;
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30 : out = 7;
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31 : out = 8;
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32 : out = 4;
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33 : out = 15;
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34 : out = 1;
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35 : out = 12;
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36 : out = 14;
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37 : out = 8;
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38 : out = 8;
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39 : out = 2;
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40 : out = 13;
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41 : out = 4;
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42 : out = 6;
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43 : out = 9;
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44 : out = 2;
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45 : out = 1;
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46 : out = 11;
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47 : out = 7;
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48 : out = 15;
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49 : out = 5;
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50 : out = 12;
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51 : out = 11;
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52 : out = 9;
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53 : out = 3;
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54 : out = 7;
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55 : out = 14;
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56 : out = 3;
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57 : out = 10;
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58 : out = 10;
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59 : out = 0;
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60 : out = 5;
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61 : out = 6;
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62 : out = 0;
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63 : out = 13;
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endcase
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end
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endmodule
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module sbox1 (in,out);
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input [5:0] in;
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output [3:0] out;
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reg [3:0] out;
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always @(in) begin
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case (in)
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0 : out = 15;
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1 : out = 3;
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2 : out = 1;
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3 : out = 13;
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4 : out = 8;
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5 : out = 4;
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6 : out = 14;
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7 : out = 7;
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8 : out = 6;
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9 : out = 15;
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10 : out = 11;
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11 : out = 2;
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12 : out = 3;
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13 : out = 8;
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14 : out = 4;
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15 : out = 14;
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16 : out = 9;
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17 : out = 12;
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18 : out = 7;
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19 : out = 0;
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20 : out = 2;
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21 : out = 1;
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22 : out = 13;
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23 : out = 10;
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24 : out = 12;
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25 : out = 6;
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26 : out = 0;
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27 : out = 9;
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28 : out = 5;
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29 : out = 11;
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30 : out = 10;
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31 : out = 5;
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32 : out = 0;
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33 : out = 13;
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34 : out = 14;
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35 : out = 8;
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36 : out = 7;
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37 : out = 10;
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38 : out = 11;
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39 : out = 1;
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40 : out = 10;
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41 : out = 3;
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42 : out = 4;
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43 : out = 15;
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44 : out = 13;
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45 : out = 4;
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46 : out = 1;
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47 : out = 2;
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48 : out = 5;
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49 : out = 11;
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50 : out = 8;
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51 : out = 6;
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52 : out = 12;
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53 : out = 7;
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54 : out = 6;
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55 : out = 12;
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56 : out = 9;
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57 : out = 0;
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58 : out = 3;
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59 : out = 5;
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60 : out = 2;
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61 : out = 14;
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62 : out = 15;
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63 : out = 9;
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endcase
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end
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endmodule
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module sbox2 (in,out);
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input [5:0] in;
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output [3:0] out;
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reg [3:0] out;
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always @(in) begin
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case (in)
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0 : out = 10;
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1 : out = 13;
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2 : out = 0;
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3 : out = 7;
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4 : out = 9;
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5 : out = 0;
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6 : out = 14;
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7 : out = 9;
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8 : out = 6;
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9 : out = 3;
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10 : out = 3;
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11 : out = 4;
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12 : out = 15;
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13 : out = 6;
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14 : out = 5;
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15 : out = 10;
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16 : out = 1;
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17 : out = 2;
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18 : out = 13;
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19 : out = 8;
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20 : out = 12;
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21 : out = 5;
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22 : out = 7;
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23 : out = 14;
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24 : out = 11;
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25 : out = 12;
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26 : out = 4;
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27 : out = 11;
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28 : out = 2;
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29 : out = 15;
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30 : out = 8;
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31 : out = 1;
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32 : out = 13;
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33 : out = 1;
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34 : out = 6;
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35 : out = 10;
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36 : out = 4;
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37 : out = 13;
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38 : out = 9;
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39 : out = 0;
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40 : out = 8;
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41 : out = 6;
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42 : out = 15;
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43 : out = 9;
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44 : out = 3;
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45 : out = 8;
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46 : out = 0;
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47 : out = 7;
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48 : out = 11;
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49 : out = 4;
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50 : out = 1;
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51 : out = 15;
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52 : out = 2;
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53 : out = 14;
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54 : out = 12;
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55 : out = 3;
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56 : out = 5;
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57 : out = 11;
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58 : out = 10;
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59 : out = 5;
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60 : out = 14;
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61 : out = 2;
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62 : out = 7;
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63 : out = 12;
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endcase
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end
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endmodule
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module sbox3 (in,out);
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input [5:0] in;
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output [3:0] out;
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reg [3:0] out;
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always @(in) begin
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case (in)
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0 : out = 7;
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1 : out = 13;
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2 : out = 13;
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3 : out = 8;
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4 : out = 14;
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5 : out = 11;
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6 : out = 3;
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7 : out = 5;
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8 : out = 0;
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9 : out = 6;
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10 : out = 6;
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11 : out = 15;
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12 : out = 9;
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13 : out = 0;
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14 : out = 10;
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15 : out = 3;
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16 : out = 1;
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17 : out = 4;
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18 : out = 2;
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19 : out = 7;
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20 : out = 8;
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21 : out = 2;
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22 : out = 5;
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23 : out = 12;
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24 : out = 11;
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25 : out = 1;
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26 : out = 12;
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27 : out = 10;
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28 : out = 4;
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29 : out = 14;
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30 : out = 15;
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31 : out = 9;
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32 : out = 10;
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33 : out = 3;
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34 : out = 6;
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35 : out = 15;
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36 : out = 9;
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37 : out = 0;
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38 : out = 0;
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39 : out = 6;
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40 : out = 12;
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41 : out = 10;
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42 : out = 11;
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43 : out = 1;
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44 : out = 7;
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45 : out = 13;
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46 : out = 13;
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47 : out = 8;
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48 : out = 15;
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49 : out = 9;
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50 : out = 1;
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51 : out = 4;
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52 : out = 3;
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53 : out = 5;
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54 : out = 14;
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55 : out = 11;
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56 : out = 5;
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57 : out = 12;
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58 : out = 2;
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59 : out = 7;
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60 : out = 8;
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61 : out = 2;
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62 : out = 4;
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63 : out = 14;
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endcase
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end
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endmodule
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module sbox4 (in,out);
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input [5:0] in;
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output [3:0] out;
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reg [3:0] out;
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always @(in) begin
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case (in)
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0 : out = 2;
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1 : out = 14;
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2 : out = 12;
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3 : out = 11;
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4 : out = 4;
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5 : out = 2;
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6 : out = 1;
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7 : out = 12;
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8 : out = 7;
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9 : out = 4;
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10 : out = 10;
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11 : out = 7;
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12 : out = 11;
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13 : out = 13;
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14 : out = 6;
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15 : out = 1;
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16 : out = 8;
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17 : out = 5;
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18 : out = 5;
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19 : out = 0;
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20 : out = 3;
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21 : out = 15;
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22 : out = 15;
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23 : out = 10;
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24 : out = 13;
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25 : out = 3;
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26 : out = 0;
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27 : out = 9;
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28 : out = 14;
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29 : out = 8;
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30 : out = 9;
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31 : out = 6;
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32 : out = 4;
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33 : out = 11;
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34 : out = 2;
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35 : out = 8;
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36 : out = 1;
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37 : out = 12;
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38 : out = 11;
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39 : out = 7;
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40 : out = 10;
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41 : out = 1;
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42 : out = 13;
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43 : out = 14;
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44 : out = 7;
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45 : out = 2;
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46 : out = 8;
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47 : out = 13;
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48 : out = 15;
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49 : out = 6;
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50 : out = 9;
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51 : out = 15;
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52 : out = 12;
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53 : out = 0;
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54 : out = 5;
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55 : out = 9;
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56 : out = 6;
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57 : out = 10;
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58 : out = 3;
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59 : out = 4;
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60 : out = 0;
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61 : out = 5;
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62 : out = 14;
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63 : out = 3;
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endcase
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end
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endmodule
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module sbox5 (in,out);
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input [5:0] in;
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output [3:0] out;
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reg [3:0] out;
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always @(in) begin
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case (in)
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0 : out = 12;
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1 : out = 10;
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2 : out = 1;
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3 : out = 15;
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4 : out = 10;
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5 : out = 4;
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6 : out = 15;
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7 : out = 2;
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8 : out = 9;
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9 : out = 7;
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10 : out = 2;
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11 : out = 12;
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12 : out = 6;
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13 : out = 9;
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14 : out = 8;
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15 : out = 5;
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16 : out = 0;
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17 : out = 6;
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18 : out = 13;
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19 : out = 1;
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20 : out = 3;
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21 : out = 13;
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22 : out = 4;
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23 : out = 14;
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24 : out = 14;
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25 : out = 0;
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26 : out = 7;
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27 : out = 11;
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28 : out = 5;
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29 : out = 3;
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30 : out = 11;
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31 : out = 8;
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32 : out = 9;
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33 : out = 4;
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34 : out = 14;
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35 : out = 3;
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36 : out = 15;
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37 : out = 2;
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38 : out = 5;
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39 : out = 12;
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40 : out = 2;
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41 : out = 9;
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42 : out = 8;
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43 : out = 5;
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44 : out = 12;
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45 : out = 15;
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46 : out = 3;
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47 : out = 10;
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48 : out = 7;
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49 : out = 11;
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50 : out = 0;
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51 : out = 14;
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52 : out = 4;
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53 : out = 1;
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54 : out = 10;
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55 : out = 7;
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56 : out = 1;
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57 : out = 6;
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58 : out = 13;
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59 : out = 0;
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60 : out = 11;
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61 : out = 8;
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62 : out = 6;
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63 : out = 13;
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endcase
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end
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endmodule
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module sbox6 (in,out);
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input [5:0] in;
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output [3:0] out;
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reg [3:0] out;
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always @(in) begin
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case (in)
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0 : out = 4;
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1 : out = 13;
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2 : out = 11;
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3 : out = 0;
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4 : out = 2;
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5 : out = 11;
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6 : out = 14;
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7 : out = 7;
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8 : out = 15;
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9 : out = 4;
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10 : out = 0;
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11 : out = 9;
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12 : out = 8;
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13 : out = 1;
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14 : out = 13;
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15 : out = 10;
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16 : out = 3;
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17 : out = 14;
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18 : out = 12;
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19 : out = 3;
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20 : out = 9;
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21 : out = 5;
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22 : out = 7;
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23 : out = 12;
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24 : out = 5;
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25 : out = 2;
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26 : out = 10;
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27 : out = 15;
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28 : out = 6;
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29 : out = 8;
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30 : out = 1;
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31 : out = 6;
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32 : out = 1;
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33 : out = 6;
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34 : out = 4;
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35 : out = 11;
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36 : out = 11;
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37 : out = 13;
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38 : out = 13;
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39 : out = 8;
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40 : out = 12;
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41 : out = 1;
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42 : out = 3;
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43 : out = 4;
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44 : out = 7;
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45 : out = 10;
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46 : out = 14;
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47 : out = 7;
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48 : out = 10;
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49 : out = 9;
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50 : out = 15;
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51 : out = 5;
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52 : out = 6;
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53 : out = 0;
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54 : out = 8;
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55 : out = 15;
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56 : out = 0;
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57 : out = 14;
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58 : out = 5;
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59 : out = 2;
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60 : out = 9;
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61 : out = 3;
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62 : out = 2;
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63 : out = 12;
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endcase
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end
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endmodule
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module sbox7 (in,out);
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input [5:0] in;
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output [3:0] out;
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reg [3:0] out;
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always @(in) begin
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case (in)
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0 : out = 13;
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1 : out = 1;
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2 : out = 2;
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3 : out = 15;
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4 : out = 8;
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5 : out = 13;
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6 : out = 4;
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7 : out = 8;
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8 : out = 6;
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9 : out = 10;
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10 : out = 15;
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11 : out = 3;
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12 : out = 11;
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13 : out = 7;
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14 : out = 1;
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15 : out = 4;
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16 : out = 10;
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17 : out = 12;
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18 : out = 9;
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19 : out = 5;
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20 : out = 3;
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21 : out = 6;
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22 : out = 14;
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23 : out = 11;
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24 : out = 5;
|
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25 : out = 0;
|
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26 : out = 0;
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27 : out = 14;
|
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28 : out = 12;
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29 : out = 9;
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30 : out = 7;
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31 : out = 2;
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32 : out = 7;
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|
33 : out = 2;
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34 : out = 11;
|
|
35 : out = 1;
|
|
36 : out = 4;
|
|
37 : out = 14;
|
|
38 : out = 1;
|
|
39 : out = 7;
|
|
40 : out = 9;
|
|
41 : out = 4;
|
|
42 : out = 12;
|
|
43 : out = 10;
|
|
44 : out = 14;
|
|
45 : out = 8;
|
|
46 : out = 2;
|
|
47 : out = 13;
|
|
48 : out = 0;
|
|
49 : out = 15;
|
|
50 : out = 6;
|
|
51 : out = 12;
|
|
52 : out = 10;
|
|
53 : out = 9;
|
|
54 : out = 13;
|
|
55 : out = 0;
|
|
56 : out = 15;
|
|
57 : out = 3;
|
|
58 : out = 3;
|
|
59 : out = 5;
|
|
60 : out = 5;
|
|
61 : out = 6;
|
|
62 : out = 8;
|
|
63 : out = 11;
|
|
endcase
|
|
end
|
|
endmodule
|
|
|
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module sboxes (in,out);
|
|
input [47:0] in;
|
|
output [31:0] out;
|
|
|
|
wire [31:0] out;
|
|
|
|
sbox7 s0 (.in(in[5:0]),.out(out[3:0]));
|
|
sbox6 s1 (.in(in[11:6]),.out(out[7:4]));
|
|
sbox5 s2 (.in(in[17:12]),.out(out[11:8]));
|
|
sbox4 s3 (.in(in[23:18]),.out(out[15:12]));
|
|
sbox3 s4 (.in(in[29:24]),.out(out[19:16]));
|
|
sbox2 s5 (.in(in[35:30]),.out(out[23:20]));
|
|
sbox1 s6 (.in(in[41:36]),.out(out[27:24]));
|
|
sbox0 s7 (.in(in[47:42]),.out(out[31:28]));
|
|
endmodule
|
|
|