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136 lines
3.7 KiB
Verilog
136 lines
3.7 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 01-24-2006
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// DES wrappers to do UNIX style 'one way' password encryption
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module ascii_to_bin (in,out);
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input [7:0] in;
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output [5:0] out;
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wire [5:0] out;
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assign out = (in>="a"?(in-59):in>="A"?(in-53):in-".");
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endmodule
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////////////////////////////
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module bin_to_ascii (in,out);
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input [5:0] in;
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output [7:0] out;
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wire [7:0] out;
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assign out = (in>=38?(in-38+"a"):in>=12?(in-12+"A"):in+".");
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endmodule
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////////////////////////////
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module salt_to_bin (in,out);
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input [15:0] in;
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output [11:0] out;
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wire [11:0] out;
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ascii_to_bin x (.in(in[15:8]),.out(out[5:0]) );
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ascii_to_bin y (.in(in[7:0]),.out(out[11:6]) );
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endmodule
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////////////////////////////
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module passwd_to_bin (in,out);
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input [63:0] in;
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output [63:0] out;
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wire [63:0] out;
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assign out = ((in & 64'h7f7f7f7f7f7f7f7f) << 1);
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endmodule
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////////////////////////////
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module des_to_string (in,out);
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input [63:0] in;
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output[87:0] out;
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wire [87:0] out;
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genvar i;
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generate
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for (i=0;i<10;i=i+1)
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begin:dtos
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bin_to_ascii b(
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.in(in[63-6*i:58-6*i]),
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.out(out[87-8*i:80-8*i])
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);
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end
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endgenerate
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bin_to_ascii l (.in({in[3:0],2'b0}),
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.out(out[7:0])
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);
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endmodule
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////////////////////////////
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// unix password crypt function
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// 25 round DES with 12 bit salt
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// salt,pass,and out are ASCII string format.
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//
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// for use in a pipeline possible to feed in 16 strings, wait, read out 16
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//
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module passwd_crypt (clk,rst,salt,pass,out,super_round,des_round);
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input clk,rst;
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input [15:0] salt;
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input [63:0] pass;
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output [87:0] out;
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output [4:0] super_round; // 0..24 full DES
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output [3:0] des_round; // 0..15 des stage within a full round
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wire [4:0] super_round;
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wire [3:0] des_round;
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wire [87:0] out;
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wire [63:0] key;
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passwd_to_bin ptob (.in(pass),.out(key));
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reg [8:0] cntr;
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assign {super_round,des_round} = cntr;
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always @(posedge clk or posedge rst) begin
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if (rst) cntr <= 9'b0;
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else begin
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if (cntr == 9'b110001111) // super 24, round 15
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cntr <= 9'b0;
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else
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cntr <= cntr + 1'b1;
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end
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end
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wire [63:0] des_out;
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wire [63:0] block_in;
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wire [11:0] salt_bin;
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salt_to_bin stob (.in(salt),.out(salt_bin));
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assign block_in = (cntr[8:4] == 5'b0 ? 64'b0 : des_out);
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des d (.clk(clk),.rst(rst),.in(block_in),
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.out(des_out),.key(key),.salt(salt_bin));
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defparam d .PIPE_16B = 1'b1;
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defparam d .USE_SALT = 1'b1;
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des_to_string dtos (.in(des_out),.out(out));
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endmodule
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