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128 lines
3.4 KiB
Systemverilog
128 lines
3.4 KiB
Systemverilog
`timescale 1 ps / 1 ps
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// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 09-22-2008
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// Test word and frame lock on a single lane TX->RX pair
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module lane_tb ();
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reg clk=0,arst=0;
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reg [64:0] din = 0;
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wire din_ack;
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wire [19:0] tx_out;
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wire [65:0] recovered; // [65]=1 indicates sync [64]=1 indicates control words
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wire recovered_valid;
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wire word_locked;
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wire sync_locked;
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wire framing_error;
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wire crc32_error;
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wire scrambler_mismatch;
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wire missing_sync;
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//////////////////////////////
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// Simple TX->RX link
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//////////////////////////////
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reg [19:0] tx_error = 20'h12345;
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wire [19:0] rx_in = tx_out | tx_error;
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lane_tx dut_t (
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.clk,.arst,
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.din,
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.din_ack,
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.dout(tx_out)
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);
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// For debugging sanity - just send everything non-inverted
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//defparam dut_t .DISABLE_DISPARITY = 1'b1;
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lane_rx dut_r (
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.clk,.arst,
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.din(rx_in),
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.dout(recovered), // [64]=1 indicates control words
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.dout_valid(recovered_valid),
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.word_locked,
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.sync_locked,
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.framing_error,
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.crc32_error,
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.scrambler_mismatch,
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.missing_sync
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);
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//////////////////////////////
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// Line monitor
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//////////////////////////////
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reg [255:0] line_history;
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always @(posedge clk) begin
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line_history <= (line_history << 8'd20) | tx_out;
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end
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//////////////////////////////
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// Stimulus
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//////////////////////////////
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initial begin
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#1 arst = 1'b1;
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@(negedge clk) arst = 1'b0;
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#1000 tx_error = 20'h00000;
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end
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always begin
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#5 clk = ~clk;
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end
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reg [15:0] error_cntr;
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reg rst_error_cntr = 0;
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always @(posedge clk) begin
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if (rst_error_cntr) error_cntr <= 0;
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else if (framing_error |crc32_error | scrambler_mismatch | missing_sync) begin
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error_cntr <= error_cntr + 1'b1;
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end
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end
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initial begin
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rst_error_cntr = 1'b1;
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#8400 if (!word_locked) begin
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$display ("Failed to acquire word lock as expected");
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$stop();
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end
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#2000 if (!sync_locked) begin
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$display ("Failed to acquire sync lock as expected");
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$stop();
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end
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rst_error_cntr = 1'b0;
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#100000
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if (error_cntr !== 0) begin
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$display ("Errors flagged during normal operation");
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$stop();
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end
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$display ("PASS");
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$stop();
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end
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always @(negedge clk) begin
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if (din_ack) din <= din + 1'b1;
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end
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endmodule |