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120 lines
4.0 KiB
Verilog
120 lines
4.0 KiB
Verilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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// baeckler - 09-24-2008
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module lane_tx_crc (
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input clk, arst,
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input [63:0] din,
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input previous_din_ack,
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input final_din_of_burst,
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input [1:0] status_bits, // to be embedded in the diagnostic word
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output reg [31:0] crc
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);
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reg [63:0] din_r;
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reg din_r_fresh;
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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din_r <= 0;
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din_r_fresh <= 1'b0;
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end
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else begin
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if (previous_din_ack) din_r <= din;
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end
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end
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wire [63:0] diag = {6'b011001,24'h000000,status_bits,32'h00000000};
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// CRC XOR networks
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wire [31:0] evolved_din;
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crc32c_dat64_only cc0 (.d(din_r),.crc_out(evolved_din));
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// this one will minimize heavily
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wire [31:0] evolved_diag;
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crc32c_dat64_only cc1 (.d(diag),.crc_out(evolved_diag));
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wire [31:0] evolved_prev;
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crc32c_zer64 cc2 (.c(crc),.crc_out(evolved_prev));
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reg [31:0] evolved_din_r, evolved_diag_r, evolved_prev_r;
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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evolved_din_r <= 0;
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evolved_diag_r <= 0;
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evolved_prev_r <= 0;
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end
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else begin
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evolved_din_r <= evolved_din;
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evolved_diag_r <= evolved_diag;
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evolved_prev_r <= evolved_prev;
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end
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end
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// this is a short cut to get 2 evolutions away from DIN faster
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wire [31:0] double_din;
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crc32c_zer64_flat cc3 (.c(evolved_din_r ^ evolved_prev_r),.crc_out(double_din));
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reg [31:0] double_din_r;
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always @(posedge clk or posedge arst) begin
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if (arst) double_din_r <= 0;
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else double_din_r <= double_din;
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end
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reg [9:0] schedule;
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wire [9:0] schedule_shl = {schedule[8:0],1'b0};
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always @(posedge clk or posedge arst) begin
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if (arst) schedule <= 10'b1;
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else begin
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if (schedule[0] & previous_din_ack) schedule <= schedule_shl;
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if (schedule[1]) schedule <= schedule_shl; // din_r is valid
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if (schedule[2]) begin // evolved din_r is valid
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if (final_din_of_burst) schedule <= schedule_shl;
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else schedule <= 10'b1;
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end
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if (schedule[3]) schedule <= schedule_shl; // double_din_r valid
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if (schedule[4]) schedule <= schedule_shl; //
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if (schedule[5]) schedule <= schedule_shl; //
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if (schedule[6]) schedule <= schedule_shl; // wait for CRC to send
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if (schedule[7]) schedule <= schedule_shl; //
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if (schedule[8]) schedule <= schedule_shl; // start next crc
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if (schedule[9]) schedule <= 10'b01;
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end
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end
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// CRC register
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always @(posedge clk or posedge arst) begin
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if (arst) crc <= 0;
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else begin
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if (schedule[8]) crc <= 32'hf8dfefd0;
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// This magic constant is the CRC of the
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// sync word, scrambler state (blanked) and skip word
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// starting from all ones.
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else if (schedule[2]) crc <= (evolved_prev_r ^ evolved_din_r);
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else if (schedule[3]) crc <= (double_din_r ^ evolved_diag_r);
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end
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end
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endmodule
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