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44 lines
1.9 KiB
Verilog
44 lines
1.9 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// compute the sum of absolute difference between 2 pairs of
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// 8 bit pixels. Output range is 0..0x1fe
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// Area cost is 27 arithmetic cells
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module pair_sad (a0,a1,b0,b1,sad);
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input [7:0] a0,a1,b0,b1;
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output [8:0] sad;
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wire [8:0] sad;
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wire [8:0] diff0 = a0 - b0;
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wire [8:0] diff1 = a1 - b1;
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wire [10:0] tmp_sum;
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double_addsub as (.a(diff0),.b(diff1),.negate_a(diff0[8]),.negate_b(diff1[8]),
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.sum(tmp_sum));
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defparam as .WIDTH = 9;
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defparam as .HW_CELLS = 1;
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assign sad = tmp_sum[8:0];
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endmodule
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