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https://github.com/pConst/basic_verilog.git
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66 lines
1.5 KiB
Verilog
66 lines
1.5 KiB
Verilog
//--------------------------------------------------------------------------------
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// UartTxExtreme.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Extreme minimal UART transmitter
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//
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// CAUTION:
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// optimized for 20MHz/115200
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// tx_busy has been made asynchronous to tx_do_sample
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// tx_start has no internal protection and should be rised only when tx_busy is low
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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reg [7:0] tx_sample_cntr = 0;
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always @ (posedge clk20) begin
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if (tx_sample_cntr[7:0] == 0) begin
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tx_sample_cntr[7:0] <= (173-1);
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end else begin
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tx_sample_cntr[7:0] <= tx_sample_cntr[7:0] - 1;
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end
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end
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wire tx_do_sample = (tx_sample_cntr[7:0] == 0);
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UartTxExtreme UT1 (
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.clk(),
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//.tx_do_sample(),
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.tx_data(),
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.tx_start(),
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.tx_busy(),
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.txd()
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module UartTxExtreme(clk, tx_do_sample, tx_data, tx_start, tx_busy, txd);
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input wire clk;
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input wire tx_do_sample;
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input wire [7:0] tx_data;
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input wire tx_start;
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output wire tx_busy;
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output reg txd = 1;
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reg [9:0] tx_shifter = 0;
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always @ (posedge clk) begin
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if (tx_start && ~tx_busy) begin
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tx_shifter[9:0] <= {1'b1,tx_data[7:0],1'b0};
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end // tx_start
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if (tx_do_sample && tx_busy) begin
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{tx_shifter[9:0],txd} <= {tx_shifter[9:0],txd} >> 1;
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end // tx_do_sample
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end
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assign
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tx_busy = (tx_shifter[9:0] != 0);
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endmodule
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