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107 lines
4.0 KiB
Verilog
107 lines
4.0 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 01-02-2007
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module adder_tree (clk,in_words,out,extra_bit_in,extra_bit_out);
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parameter NUM_IN_WORDS = 5;
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parameter NUM_IN_PAIRS = NUM_IN_WORDS / 2;
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parameter NUM_IN_ODD = NUM_IN_WORDS - NUM_IN_PAIRS * 2;
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parameter BITS_PER_IN_WORD = 13;
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parameter OUT_BITS = 29;
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parameter SIGN_EXT = 1; // bool - sign vs 0 extend
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parameter REGISTER_MIDDLE = 0; // bool - register within adders or not
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parameter REGISTER_OUTPUT = 1; // bool - register adder outputs or not
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parameter SHIFT_DIST = 1; // for multiplication - a shift between words
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parameter EXTRA_BIT_USED = 0; // extra bit to pass along the pipeline
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// properties of the 1st layer output
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// Guess the number of output bits, if the guess is more than
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// the final requirement cap it.
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parameter LAYER_OUT_WORDS = NUM_IN_PAIRS + NUM_IN_ODD;
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parameter LAYER_OUT_EST_BITS = BITS_PER_IN_WORD + 1 + SHIFT_DIST;
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parameter LAYER_OUT_BITS = (OUT_BITS < LAYER_OUT_EST_BITS) ? OUT_BITS : LAYER_OUT_EST_BITS;
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input clk;
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input extra_bit_in;
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output extra_bit_out;
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input [NUM_IN_WORDS*BITS_PER_IN_WORD-1:0] in_words;
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output [OUT_BITS-1:0] out;
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generate
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if (NUM_IN_WORDS == 1) begin
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if (OUT_BITS > BITS_PER_IN_WORD) begin
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// the output needs to be extended more
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initial begin
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$display ("Excess output width not currently supported");
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$stop();
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end
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end
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// no more pipe, just tie off the wires and terminate recursion
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assign out = in_words;
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assign extra_bit_out = extra_bit_in;
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end
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else begin
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// knock out one horizontal slice of pairs
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wire [LAYER_OUT_WORDS*LAYER_OUT_BITS-1:0] layer_out;
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wire next_extra_bit;
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adder_tree_layer al (
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.clk(clk),
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.in_words(in_words),
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.out_words(layer_out),
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.extra_bit_in(extra_bit_in),
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.extra_bit_out(next_extra_bit)
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);
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defparam al .NUM_IN_WORDS = NUM_IN_WORDS;
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defparam al .BITS_PER_IN_WORD = BITS_PER_IN_WORD;
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defparam al .BITS_PER_OUT_WORD = LAYER_OUT_BITS;
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defparam al .SIGN_EXT = SIGN_EXT;
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defparam al .REGISTER_OUTPUT = REGISTER_OUTPUT;
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defparam al .REGISTER_MIDDLE = REGISTER_MIDDLE;
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defparam al .SHIFT = SHIFT_DIST;
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defparam al .EXTRA_BIT_CONNECTED = EXTRA_BIT_USED;
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// recurse on the remaining words
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adder_tree at (
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.clk(clk),
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.in_words(layer_out),
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.out(out),
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.extra_bit_in(next_extra_bit),
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.extra_bit_out(extra_bit_out)
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);
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defparam at .NUM_IN_WORDS = LAYER_OUT_WORDS;
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defparam at .BITS_PER_IN_WORD = LAYER_OUT_BITS;
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defparam at .OUT_BITS = OUT_BITS;
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defparam at .SIGN_EXT = SIGN_EXT;
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defparam at .REGISTER_OUTPUT = REGISTER_OUTPUT;
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defparam at .REGISTER_MIDDLE = REGISTER_MIDDLE;
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defparam at .SHIFT_DIST = SHIFT_DIST * 2;
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defparam at .EXTRA_BIT_USED = EXTRA_BIT_USED;
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end
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endgenerate
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endmodule
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