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105 lines
3.3 KiB
Verilog
105 lines
3.3 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 01-02-2007
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// a relatively fancy adder tree node
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module adder_tree_node (clk,a,b,out);
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parameter IN_BITS = 16;
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parameter OUT_BITS = 17;
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parameter SIGN_EXT = 1;
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parameter REGISTER_MIDDLE = 0; // register within adder chains
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parameter REGISTER_OUTPUT = 1; // register adder outputs
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parameter B_SHIFT = 1;
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// for the placement of the midway pipeline registers
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localparam LS_WIDTH = OUT_BITS / 2;
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localparam MS_WIDTH = OUT_BITS - LS_WIDTH;
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input clk;
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input [IN_BITS-1:0] a,b;
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output [OUT_BITS-1:0] out;
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// sign extension
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wire [OUT_BITS-1:0] a_ext,b_ext;
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generate
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if (SIGN_EXT) begin
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assign a_ext = {{(OUT_BITS-IN_BITS){a[IN_BITS-1]}},a};
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assign b_ext = {{(OUT_BITS-IN_BITS){b[IN_BITS-1]}},b};
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end
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else begin
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assign a_ext = {{(OUT_BITS-IN_BITS){1'b0}},a};
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assign b_ext = {{(OUT_BITS-IN_BITS){1'b0}},b};
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end
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endgenerate
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// offset B
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wire [OUT_BITS-1:0] b_ext_shft;
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assign b_ext_shft = b_ext << B_SHIFT;
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// addition
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wire [OUT_BITS-1:0] sum;
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generate
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if (REGISTER_MIDDLE) begin
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// pipeline in the middle of the adder chain
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reg [LS_WIDTH-1+1:0] ls_adder;
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wire cross_carry = ls_adder[LS_WIDTH];
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always @(posedge clk) begin
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ls_adder <= {1'b0,a_ext[LS_WIDTH-1:0]} + {1'b0,b_ext_shft[LS_WIDTH-1:0]};
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end
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reg [MS_WIDTH-1:0] ms_data_a,ms_data_b;
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always @(posedge clk) begin
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ms_data_a <= a_ext[OUT_BITS-1:OUT_BITS-MS_WIDTH];
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ms_data_b <= b_ext_shft[OUT_BITS-1:OUT_BITS-MS_WIDTH];
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end
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wire [MS_WIDTH-1+1:0] ms_adder;
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assign ms_adder = {ms_data_a,cross_carry} +
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{ms_data_b,cross_carry};
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assign sum = {ms_adder[MS_WIDTH:1],ls_adder[LS_WIDTH-1:0]};
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end
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else begin
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// simple addition
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assign sum = a_ext + b_ext_shft;
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end
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endgenerate
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// optional output register
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reg [OUT_BITS-1:0] out;
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generate
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if (REGISTER_OUTPUT) begin
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always @(posedge clk) begin
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out <= sum;
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end
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end
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else begin
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always @(*) begin
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out = sum;
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end
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end
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endgenerate
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endmodule |