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88 lines
3.2 KiB
Verilog
88 lines
3.2 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 09-01-2006
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//
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// Example of adder using 2 carry chains, with the carry between them on standard
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// routing. This technique is useful when very long chains are causing placement
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// difficulty. Should use exactly WIDTH+2 cells.
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module split_add (a,b,o);
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parameter LS_WIDTH = 10;
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parameter MS_WIDTH = 10;
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parameter WIDTH = LS_WIDTH + MS_WIDTH;
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input [WIDTH-1:0] a,b;
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output [WIDTH-1:0] o;
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wire [WIDTH-1:0] o;
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// Build the less significant adder with an extra bit on the top to get
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// the carry chain onto the normal routing. The keep pragma prevents
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// synthesis from undoing the split.
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wire [LS_WIDTH-1+1:0] ls_adder;
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wire cross_carry = ls_adder[LS_WIDTH] /* synthesis keep */;
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assign ls_adder = {1'b0,a[LS_WIDTH-1:0]} + {1'b0,b[LS_WIDTH-1:0]};
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// Build the more significant adder with an extra low bit to incorporate
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// the carry from the split lower chain.
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wire [MS_WIDTH-1+1:0] ms_adder;
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assign ms_adder = {a[WIDTH-1:WIDTH-MS_WIDTH],cross_carry} +
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{b[WIDTH-1:WIDTH-MS_WIDTH],cross_carry};
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// collect the sum back together, drop the two internal bits
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assign o = {ms_adder[MS_WIDTH:1],ls_adder[LS_WIDTH-1:0]};
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endmodule
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/////////////////////////////////
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module split_add_tb ();
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parameter LS_WIDTH = 15;
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parameter MS_WIDTH = 20;
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parameter WIDTH = LS_WIDTH + MS_WIDTH;
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reg [WIDTH-1:0] a,b;
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wire [WIDTH-1:0] oa,ob;
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assign ob = a + b; // functional model
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split_add s (.a(a),.b(b),.o(oa));
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defparam s .LS_WIDTH = LS_WIDTH;
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defparam s .MS_WIDTH = MS_WIDTH;
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always begin
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#100
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a = {$random,$random};
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b = {$random,$random};
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#10 if (oa !== ob) begin
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$display ("Mismatch at time %d",$time);
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$stop();
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end
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end
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initial begin
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#1000000 $display ("PASS");
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$stop();
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end
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endmodule |