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basic_verilog/gitignores/.gitignore_modelsim
2022-05-16 18:58:36 +03:00

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#------------------------------------------------------------------------------
# .gitignore for Mentor Modelsim
# published as part of https://github.com/pConst/basic_verilog
# Konstantin Pavlov, pavlovconst@gmail.com
#------------------------------------------------------------------------------
# INFO ------------------------------------------------------------------------
# rename the file to ".gitignore" and place into your testbench directory
#
transcript
work*
modelsim.ini
start_time.txt
vsim.wlf