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83 lines
1.9 KiB
Systemverilog
83 lines
1.9 KiB
Systemverilog
//------------------------------------------------------------------------------
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// delay.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO -------------------------------------------------------------------------
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// Static Delay for arbitrary signal
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// Another equivalent names for this module:
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// conveyor.sv
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// synchronizer.sv
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//
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// Tip for Xilinx-based implementations: Leave nrst=1'b1 and ena=1'b1 on
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// purpose of inferring Xilinx`s SRL16E/SRL32E primitives
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//
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//
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// CAUTION: delay module is widely used for synchronizing signals across clock
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// domains. To automatically exclude input data paths from timing analisys
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// set_false_path SDC constraint is integrated into this module. Applicable
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// only to Intel/Altera Quartus IDE. Xilinx users still should write the
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// constraints manually
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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delay #(
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.LENGTH( 2 )
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) S1 (
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.clk( clk ),
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.nrst( 1'b1 ),
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.ena( 1'b1 ),
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.in( ),
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.out( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module delay #( parameter
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LENGTH = 2 // delay/synchronizer chain length
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// default length for synchronizer chain is 2
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)(
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input clk,
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input nrst,
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input ena,
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input in,
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output out
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);
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generate
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if ( LENGTH == 0 ) begin
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assign out = in;
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end else if( LENGTH == 1 ) begin
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logic data = 0;
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always_ff @(posedge clk) begin
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if (~nrst) begin
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data <= 0;
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end else if (ena) begin
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data <= in;
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end
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end
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assign out = data;
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end else begin
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logic [LENGTH:1] data = 0;
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always_ff @(posedge clk) begin
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if (~nrst) begin
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data[LENGTH:1] <= 0;
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end else if (ena) begin
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data[LENGTH:1] <= {data[LENGTH-1:1],in};
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end
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end
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assign out = data[LENGTH];
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end // if
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endgenerate
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endmodule
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