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76 lines
2.1 KiB
Verilog
76 lines
2.1 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module seconds_counter_tb ();
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parameter WIDTH = 8;
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reg rst = 0, clk = 0;
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wire [WIDTH-1:0] val;
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wire tick;
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seconds_counter sc
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(
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.clk100(clk),
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.reset(rst),
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.count_val(val),
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.tick(tick)
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);
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defparam sc .WIDTH = WIDTH;
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integer check = 0;
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reg fail = 0;
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initial begin
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@(negedge clk) rst = 1'b1;
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@(negedge clk) rst = 1'b0;
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check = 0;
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@(posedge tick);
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@(negedge clk);
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@(negedge clk);
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$display ("check = %d",check);
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if (val != 1) begin
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$display ("Mismatch in seconds counter");
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fail = 1;
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end
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if (check !== 100_000_001) begin
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$display ("Mismatch with cycle count");
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fail = 1;
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end
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@(negedge clk);
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if (!fail) $display ("PASS");
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$stop();
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end
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always @(posedge clk) begin
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check <= check + 1'b1;
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end
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always begin
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#5 clk = ~clk;
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end
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endmodule |